&8(R xiaomi,ax3000tmediatek,mt7981b +7Xiaomi AX3000Tcpus+cpu@0arm,cortex-a53=AcpuMpscicpu@1arm,cortex-a53=AcpuMpscioscillator-40m fixed-clock[bZkclkxtal~psci arm,psci-1.0Tsmcsoc simple-bus+interrupt-controller@c000000 arm,gic-v3 =      clock-controller@10001000 mediatek,mt7981-infracfgsyscon=~clock-controller@1001b000 mediatek,mt7981-topckgensyscon=~watchdog@1001c000mediatek,mt7986-wdt= nclock-controller@1001e000mediatek,mt7981-apmixedsys=~pwm@10048000mediatek,mt7981-pwm=( topmainpwm1pwm2pwm3serial@11002000*mediatek,mt7981-uartmediatek,mt6577-uart=  { uartwakeup baudbus disabledserial@11003000*mediatek,mt7981-uartmediatek,mt6577-uart=0 | uartwakeup  baudbus disabledserial@11004000*mediatek,mt7981-uartmediatek,mt6577-uart=@ } uartwakeup! baudbus disabledi2c@11007000mediatek,mt7981-i2c =p!p  34maindmaarbpmic+ disabledspi@11009000)mediatek,mt7981-spi-ipmmediatek,spi-ipm=  N"# parent-clksel-clkspi-clkhclk+ disabledspi@1100a000)mediatek,mt7981-spi-ipmmediatek,spi-ipm=  N') parent-clksel-clkspi-clkhclk+ disabledspi@1100b000)mediatek,mt7981-spi-ipmmediatek,spi-ipm=  N(* parent-clksel-clkspi-clkhclk+ disabledpinctrl@11d00000mediatek,mt7981-pinctrl=I gpioiocfg_rtiocfg_rmiocfg_rbiocfg_lbiocfg_bliocfg_tmiocfg_tleint  8#3efuse@11f20000%mediatek,mt7981-efusemediatek,efuse=+clock-controller@15000000mediatek,mt7981-ethsyssyscon=~wifi@18000000mediatek,mt7981-wmac0=00_\ mcuap2conn?Fconsystimerarm,armv8-timer 0   memory@40000000=@Amemory compatibleinterrupt-parent#address-cells#size-cellsmodelregdevice_typeenable-methodclock-frequencyclock-output-names#clock-cellsrangesinterruptsinterrupt-controller#interrupt-cellsphandle#reset-cellsclocksclock-names#pwm-cellsinterrupt-namesstatusreg-namesgpio-rangesgpio-controller#gpio-cellsresetsreset-names