Q8(y4mediatek,mt8390-evkmediatek,mt8390mediatek,mt8188 +7MediaTek Genio-700 EVKcpus+cpu@0=cpuarm,cortex-a55IMpsci[w5k~@@cpu@100=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@200=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@300=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@400=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@500=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@600=cpuarm,cortex-a78IMpsci[k~@@cpu@700=cpuarm,cortex-a78IMpsci[k~@@cpu-mapcluster0core0core1 core2 core3 core4 core5 core6core7idle-statespscicpu-off-larm,idle-state6G2X_hDcpu-off-barm,idle-state6G-Xhcluster-off-larm,idle-state6G7XhHcluster-off-barm,idle-state6G2Xhl2-cache0cachey@l2-cache1cachey@l3-cachecachey @oscillator-13m fixed-clock[]@clk13m0oscillator-26m fixed-clock[clk26m2oscillator-32k fixed-clock[clk32kopp-table-gpuoperating-points-v2Wopp-390000000>opp-431000000opp-4730000001h@ 'opp-515000000F Xopp-556000000!# hopp-598000000# <opp-640000000&% opp-670000000'c opp-700000000)' Lopp-730000000+ }opp-760000000-L `opp-790000000/q 4opp-8350000001 (ropp-8800000004s qopp-9150000006 Xopp-915000000-56 0opp-915000000-66 qpopp-9500000008ـ 5opp-950000000-58ـ X0opp-950000000-68ـ qppmu-a55arm,cortex-a55-pmu pmu-a78arm,cortex-a78-pmu psci arm,psci-1.0Tsmcthermal-zonescpu-little0-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0:H? cpu-little1-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0:H? cpu-little2-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0:H? cpu-little3-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0:H? cpu-big0-thermaldtripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0:?cpu-big1-thermaldtripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0:?apu-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalgpu-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0: ?gpu1-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0: ?adsp-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalvdo-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalinfra-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcam1-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcam2-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticaltimerarm,armv8-timer @   []@soc+ simple-busNinterrupt-controller@c000000 arm,gic-v3Uf } I    ppi-partitionsinterrupt-partition-0 interrupt-partition-1syscon@10000000 mediatek,mt8188-topckgensysconIsyscon@10001000#mediatek,mt8188-infracfg-aosysconI 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+cpower-domain@32I w&'($~ss-camb-subss-camb-rawss-camb-yuvcpower-domain@31Iw&)*$~ss-cama-subss-cama-rawss-cama-yuvcpower-domain@17I(w+++&~cfgckcfgxoss-larb2ss-larb3ss-gals +cpower-domain@9I w@? ~bushdcp cpower-domain@18I cpower-domain@19I cpower-domain@24I w,,,,0~ss-ve1-larbss-ve1-coress-ve1-galsss-ve1-sram cpower-domain@21Iw--~ss-wpe-l7ss-wpe-l7pce cpower-domain@5I w. ~ss-pextp-fmemcpower-domain@7Iw01~seninf0seninf1cpower-domain@6Icpower-domain@10I wED ~busmain +cpower-domain@11I  +cpower-domain@14IwF~asm cpower-domain@13I wS/~a1sysintbusadspck cpower-domain@12I  cpower-domain@8Iw.  ~ethermac cwatchdog@10007000mediatek,mt8188-wdtIpsyscon@1000c000"mediatek,mt8188-apmixedsyssysconIRtimer@10017000,mediatek,mt8188-timermediatek,mt6765-timerIp w0pwrap@100240003mediatek,mt8188-pwrapmediatek,mt8195-pwrapsysconI@pwrapw   ~spiwrappmicmediatek,mt6359}U adcmediatek,mt6359-auxadcmt6359codecregulatorsbuck_vs1vs1 5!-Ibuck_vgpu11vgpu117]- rIbuck_vmodemvmodem]*-buck_vpuvpu7]- rIbuck_vcorevcore ]- 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scp@10500000mediatek,mt8188-scp IPr sramcfg1okayclock-controller@10b91100mediatek,mt8188-adsp-audio26mI/serial@11001100*mediatek,mt8188-uartmediatek,mt6577-uartI w2  ~baudbusokay3defaultserial@11001200*mediatek,mt8188-uartmediatek,mt6577-uartI w2  ~baudbusokay4defaultserial@11001300*mediatek,mt8188-uartmediatek,mt6577-uartI w2  ~baudbusokay5defaultserial@11001400*mediatek,mt8188-uartmediatek,mt6577-uartI w2  ~baudbus disabledadc@11002000.mediatek,mt8188-auxadcmediatek,mt8173-auxadcI w ~main disabledsyscon@11003000"mediatek,mt8188-pericfg-aosysconI0.spi@1100a000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+Iwy ~parent-clksel-clkspi-clk disabledthermal-sensor@1100b000mediatek,mt8188-lvts-apI w  6lvts-calib-data-1spi@11010000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+Iwy 2~parent-clksel-clkspi-clk disabledspi@11012000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+I wy 3~parent-clksel-clkspi-clkokay7defaultspi@11013000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+I0wy 4~parent-clksel-clkspi-clk disabledspi@11018000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+Iwy 8~parent-clksel-clkspi-clk disabledspi@11019000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+Iwy 9~parent-clksel-clkspi-clk disabledusb@11200000'mediatek,mt8188-xhcimediatek,mtk-xhci I  > macippc89)*&vvw. . ~sys_ckref_ckmcu_ck =:hTokayb;p<mmc@11230000(mediatek,mt8188-mmcmediatek,mt8183-mmc I# w   M!~sourcehclksource_cgcrypto_clkokaydefaultstate_uhs=|> H ?@"mmc@11240000(mediatek,mt8188-mmcmediatek,mt8183-mmc I$w  $~sourcehclksource_cg&okaydefaultstate_uhsA|B 0AN\ c CDthermal-sensor@11278000mediatek,mt8188-lvts-mcuI'w  6lvts-calib-data-1i2c@11280000mediatek,mt8188-i2c I("lwE 7 ~maindma+okaydefaultF[touchscreen@5dgoodix,gt9271I]  v  GHdefaultIi2c@11281000mediatek,mt8188-i2c I("lwE 7 ~maindma+okaydefaultJ[i2c@11282000mediatek,mt8188-i2c I( "lwE 7 ~maindma+okaydefaultK[clock-controller@11283000mediatek,mt8188-imp-iic-wrap-cI(0Eusb@112a0000'mediatek,mt8188-xhcimediatek,mtk-xhci I**> macippcL.-&vvw..~sys_ckref_ckmcu_ckokayb;usb@112b0000'mediatek,mt8188-xhcimediatek,mtk-xhci I++> macippcM,+&vvw..~sys_ckref_ckmcu_ck =:`Tokayb;spi@1132c000(mediatek,mt8188-normediatek,mt8186-norI2wX.. ~spisfaxiX9 disabledi2c@11e00000mediatek,mt8188-i2c I"lwN 7 ~maindma+okaydefaultO[i2c@11e01000mediatek,mt8188-i2c I"lwN 7 ~maindma+okaydefaultP|Q[B@clock-controller@11e02000mediatek,mt8188-imp-iic-wrap-wI Nt-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+Nokayusb-phy@0IwR ~refda_refMt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+Nokayusb-phy@0IwR ~refda_ref8usb-phy@700I wR2 ~refda_ref disabled9t-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+Nokayusb-phy@0IwR ~refda_refLi2c@11ec0000mediatek,mt8188-i2c I"lwS 7 ~maindma+okaydefaultT[i2c@11ec1000mediatek,mt8188-i2c I"lwS 7 ~maindma+okaydefaultU[clock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-enI Sefuse@11f20000%mediatek,mt8188-efusemediatek,efuseI+lvts1-calib@1acI@6gpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jmI@wV0~} jobmmugpuWXXXcore0core1core2 disabledclock-controller@13fbf000mediatek,mt8188-mfgcfgIVclock-controller@14000000mediatek,mt8188-vppsys0I!clock-controller@14e00000mediatek,mt8188-wpesysI-clock-controller@14e02000mediatek,mt8188-wpesys-vpp0I clock-controller@14f00000mediatek,mt8188-vppsys1I#clock-controller@15000000mediatek,mt8188-imgsysIclock-controller@15110000 mediatek,mt8188-imgsys1-dip-topIclock-controller@15130000mediatek,mt8188-imgsys1-dip-nrIclock-controller@15220000mediatek,mt8188-imgsys-wpe1I"clock-controller@15330000mediatek,mt8188-ipesysI3clock-controller@15520000mediatek,mt8188-imgsys-wpe2IRclock-controller@15620000mediatek,mt8188-imgsys-wpe3Ibclock-controller@16000000mediatek,mt8188-camsysI&clock-controller@1604f000mediatek,mt8188-camsys-rawaI)clock-controller@1606f000mediatek,mt8188-camsys-yuvaI*clock-controller@1608f000mediatek,mt8188-camsys-rawbI'clock-controller@160af000mediatek,mt8188-camsys-yuvbI (clock-controller@17200000mediatek,mt8188-ccusysI clock-controller@1800f000mediatek,mt8188-vdecsys-socI%clock-controller@1802f000mediatek,mt8188-vdecsysI$clock-controller@1a000000mediatek,mt8188-vencsysI,syscon@1c01d000mediatek,mt8188-vdosys0sysconI  YY"syscon@1c100000mediatek,mt8188-vdosys1sysconI  YY+aliases*/soc/serial@11001100chosen2serial0:921600n8firmwareopteelinaro,optee-tzTsmcmemory@40000000=memoryI@reserved-memory+Noptee@43200000>IC memory@50000000shared-dma-poolIP>1memory@54600000>IT` memory@55000000shared-dma-poolIU@memory@57000000shared-dma-poolIW@regulator-0regulator-fixed5v_enLK@LK@ E JIregulator-1regulator-fixededp_panel_3v32Z2ZJ EdefaultZregulator-2regulator-fixed gpio_3v3_en2Z2Z E JIregulator-3regulator-fixedsdio_iow@w@JIregulator-4regulator-fixed sdio_card2Z2Z EJJIregulator-5regulator-fixed touch_3v32Z2Z EwJGregulator-6regulator-fixed usb_hub_3v32Z2Z Ep]'J[regulator-7regulator-fixedusb_hub_resetw@w@ En[<regulator-8regulator-fixed usb_p0_vbusLK@LK@ ETJregulator-9regulator-fixed usb_p1_vbusLK@LK@ EWJregulator-10regulator-fixed usb_p2_vbusLK@LK@J compatibleinterrupt-parent#address-cells#size-cellsmodeldevice_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptspolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-deviceranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-upoutput-highdrive-strengthinput-enableinput-disablebias-disabledrive-strength-microampbias-pull-downoutput-low#power-domain-cellsclocksclock-namesmediatek,infracfgmediatek,disable-extrst#io-channel-cellsmediatek,mic-type-0mediatek,mic-type-1regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#mbox-cellsmemory-regionstatuspinctrl-0pinctrl-namesresetsnvmem-cellsnvmem-cell-names#thermal-sensor-cellsmediatek,pad-selectphysassigned-clocksassigned-clock-parentsmediatek,syscon-wakeupwakeup-sourcevusb33-supplyvbus-supplypinctrl-1bus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqecap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmccd-gpiosclock-divinterrupts-extendedirq-gpiosreset-gpiosAVDD28-supplyVDDIO-supply#phy-cellsinterrupt-namesoperating-points-v2power-domainspower-domain-namesmboxesmediatek,gce-client-regserial0stdout-pathno-mapgpioenable-active-highstartup-delay-usvin-supply