8( =firefly,px30-jd4-core-mbfirefly,px30-jd4-corerockchip,px30 +/7Firefly Core-PX30-JD4 on MB-JD4-PX30 baseboardaliases=/i2c@ff180000B/i2c@ff190000G/i2c@ff1a0000L/i2c@ff1b0000Q/serial@ff030000Y/serial@ff158000a/serial@ff160000i/serial@ff168000q/serial@ff170000y/serial@ff178000/spi@ff1d0000/spi@ff1d8000/ethernet@ff360000/mmc@ff370000/mmc@ff380000/mmc@ff390000cpus+cpu@0cpuarm,cortex-a35psciZ!cpu@1cpuarm,cortex-a35psciZ!cpu@2cpuarm,cortex-a35psciZ! cpu@3cpuarm,cortex-a35psciZ! idle-states)pscicpu-sleeparm,idle-state6G^xo!cluster-sleeparm,idle-state6G^o!opp-table-0operating-points-v2!opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem  disabledexternal-gmac-clock fixed-clock gmac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal(>L^ tripstrip-point-0npzpassivetrip-point-1nLzpassive!soc-critn8z criticalcooling-mapsmap0 gpu-thermal(d>^ tripsgpu-thresholdnpzpassivegpu-targetnLzpassive!gpu-critn8z criticalcooling-mapsmap0 xin24m fixed-clockn6xin24m!npower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+!ppower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"#power-domain@14I$syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd+!io-domains$rockchip,px30-pmu-io-voltage-domainokay%%reboot-modesyscon-reboot-modeRBRB RBRBRBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart &&(baudclkapb_pclk4''9txrxCMZdefault h()* disabledi2s@ff060000rockchip,px30-i2s-tdm  (mclk_txmclk_rxhclk4''9txrxr+ tx-mrx-mZdefault0h,-./01234567 disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  (i2s_clki2s_hclk4''9txrxZdefaulth89:; disabledi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s (i2s_clki2s_hclk4''9txrxZdefaulth<=>? disabledinterrupt-controller@ff131000 arm,gic-400@ @ `   !syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+!+io-domains rockchip,px30-io-voltage-domainokay@AB%B@lvdsrockchip,px30-lvdsC"dphyr+,lvds disabledports+port@0+endpoint@0<D!endpoint@1<E!port@1serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart I(baudclkapb_pclk4''9txrxCMZdefault hFGH disabledserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart J(baudclkapb_pclk4''9txrxCMZdefaulthIokayserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart K(baudclkapb_pclk4''9txrxCMZdefault hJKL disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart L(baudclkapb_pclk4'' 9txrxCMZdefault hMNO disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart M(baudclkapb_pclk4' ' 9txrxCMZdefault hPQR disabledi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN (i2cpclk ZdefaulthS+okaypmic@20rockchip,rk809  TZdefaulthULmxin32k{VVVVWWWWVregulatorsDCDC_REG1vdd_log~p&q;O!regulator-state-memay~DCDC_REG2vdd_arm~p&q;O!regulator-state-memy~DCDC_REG3vcc_ddr;Oregulator-state-memaDCDC_REG4vcc_3v0--;O!Bregulator-state-memay-DCDC_REG5 vcc3v3_sys2Z2Z;O!Wregulator-state-memay2ZLDO_REG1vcc_1v0B@B@;Oregulator-state-memayB@LDO_REG2vcc_1v8w@w@;O!@regulator-state-memayw@LDO_REG3vdd_1v0B@B@;Oregulator-state-memayB@LDO_REG4 vcc3v0_pmu--;O!%regulator-state-memay-LDO_REG5 vccio_sdw@2Z;O!Aregulator-state-memay2ZLDO_REG6vcc_sd2Z2ZO!zregulator-state-memay2ZLDO_REG7 vcc2v8_dvp**Oregulator-state-memy*LDO_REG8 vcc1v8_dvpw@w@Oregulator-state-memayw@LDO_REG9 vcc1v5_dvp``Oregulator-state-memy`SWITCH_REG1 vcc3v3_lcdOSWITCH_REG2 vcc5v0_host;Oi2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO (i2cpclk ZdefaulthX+ disabledi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP (i2cpclk  ZdefaulthY+ disabledi2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q (i2cpclk  ZdefaulthZ+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $U(spiclkapb_pclk4' ' 9txrxZdefaulth[\]^+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %V(spiclkapb_pclk4''9txrxZdefaulth_`abc+ disabledwatchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ % disabledpwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthd disabledpwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthe disabledpwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthf disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S (pwmpclkZdefaulthg disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthh disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthi disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthj disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T (pwmpclkZdefaulthk disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& (pclktimerdma-controller@ff240000arm,pl330arm,primecell$@ (apb_pclk!'tsadc@ff280000rockchip,px30-tsadc( $,P,X(tsadcapb_pclk tsadc-apbr+Zinitdefaultsleephlm(l2okayH_! saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( Tz-W(saradcapb_pclk saradc-apbokay@!nvmem@ff290000rockchip,px30-otp)@/Za(otpapb_pclkphyphy+id@7cpu-leakage@17performance@1eclock-controller@ff2b0000rockchip,px30-cru+ n& (xin24mgpllr+8@IFq рр !clock-controller@ff2bc000rockchip,px30-pmucru+n(xin24mr+&&& G!&syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy & (phyclko usb480m_phyokay!ohost-port D linestateokay!rotg-port$BA@otg-bvalidotg-idlinestateokay!qphy@ff2e0000rockchip,px30-dsi-dphy.& E (refpclk>apbp  disabled!Cphy@ff2f0000rockchip,px30-csi-dphy/@F(pclkp /apbr+ disabled!usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >(otgotg@ q "usb2-phypokayusb@ff340000 generic-ehci4 <r"usbpokayusb@ff350000 generic-ohci5 =r"usbpokayethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[(stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedr+"rmiiZdefaulthstp ^ stmmacethokay+output8B Cu S iPPmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CD(biuciuciu-driveciu-sample~рZdefaulthvwxypokay  zAmmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EF(biuciuciu-driveciu-sample~рZdefault h{|}p okay$:H~mmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GH(biuciuciu-driveciu-sample~рZdefault hp okayS:H B@spi@ff3a0000 rockchip,sfc:@ 8:(clk_sfchclk_sfc hZdefaultp  disablednand-controller@ff3b0000rockchip,px30-nfc;@ 97(ahbnfc7рZdefault hp  disabledopp-table-1operating-points-v2!opp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuIpokayb!video-codec@ff442000rockchip,px30-vpuD PO vepuvdpu (aclkhclknp iommu@ff442800rockchip,iommuD( Q (aclkifaceup !dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsiE KD(pclkC"dphyp =apbr++ disabledports+port@0+endpoint@0<!endpoint@1<!port@1vop@ff460000rockchip,px30-vop-bigF M(aclk_vopdclk_vophclk_vop345 axiahbdclknp  disabledport+! endpoint@0<!endpoint@1<!Diommu@ff460f00rockchip,iommuF M (aclkifacep u disabled!vop@ff470000rockchip,px30-vop-litG N(aclk_vopdclk_vophclk_vop789 axiahbdclknp  disabledport+! endpoint@0<!endpoint@1<!Eiommu@ff470f00rockchip,iommuG N (aclkifacep u disabled!isp@ff4a0000rockchip,px30-cif-ispJ$FIJ ispmimipi 3_(ispaclkhclkpclkn"dphyp  disabledports+port@0+iommu@ff4a8000rockchip,iommuJ F (aclkifacep u!qos@ff518000rockchip,px30-qossysconQ !qos@ff520000rockchip,px30-qossysconR !$qos@ff52c000rockchip,px30-qossysconR !qos@ff538000rockchip,px30-qossysconS !qos@ff538080rockchip,px30-qossysconS !qos@ff538100rockchip,px30-qossysconS !qos@ff538180rockchip,px30-qossysconS !qos@ff540000rockchip,px30-qossysconT !qos@ff540080rockchip,px30-qossysconT !qos@ff548000rockchip,px30-qossysconT !qos@ff548080rockchip,px30-qossysconT ! qos@ff548100rockchip,px30-qossysconT !!qos@ff548180rockchip,px30-qossysconT !"qos@ff548200rockchip,px30-qossysconT !#qos@ff550000rockchip,px30-qossysconU !qos@ff550080rockchip,px30-qossysconU !qos@ff550100rockchip,px30-qossysconU !qos@ff550180rockchip,px30-qossysconU !qos@ff558000rockchip,px30-qossysconU !qos@ff558080rockchip,px30-qossysconU !pinctrlrockchip,px30-pinctrlr++gpio@ff040000rockchip,gpio-bank &!Tgpio@ff250000rockchip,gpio-bank% \!gpio@ff260000rockchip,gpio-bank& ]!ugpio@ff270000rockchip,gpio-bank' ^pcfg-pull-up!pcfg-pull-downpcfg-pull-none!pcfg-pull-none-2mapcfg-pull-up-2mapcfg-pull-up-4ma!pcfg-pull-none-4mapcfg-pull-down-4mapcfg-pull-none-8ma!pcfg-pull-up-8ma!pcfg-pull-none-12ma !pcfg-pull-up-12ma !pcfg-pull-none-smt !pcfg-output-high pcfg-output-low &pcfg-input-high 1!pcfg-input 1i2c0i2c0-xfer > !Si2c1i2c1-xfer >!Xi2c2i2c2-xfer >!Yi2c3i2c3-xfer >  !Ztsadctsadc-otp-pin >!ltsadc-otp-out >!muart0uart0-xfer >  !(uart0-cts > !)uart0-rts > !*uart1uart1-xfer >!Fuart1-cts >!Guart1-rts >!Huart2-m0uart2m0-xfer >uart2-m1uart2m1-xfer > !Iuart3-m0uart3m0-xfer >uart3m0-cts >uart3m0-rts >uart3-m1uart3m1-xfer >!Juart3m1-cts > !Kuart3m1-rts > !Luart4uart4-xfer >!Muart4-cts >!Nuart4-rts >!Ouart5uart5-xfer >!Puart5-cts >!Quart5-rts >!Rspi0spi0-clk >![spi0-csn >!\spi0-miso > !]spi0-mosi > !^spi0-clk-hs >spi0-miso-hs > spi0-mosi-hs > spi1spi1-clk >!_spi1-csn0 > !`spi1-csn1 > !aspi1-miso >!bspi1-mosi > !cspi1-clk-hs >spi1-miso-hs >spi1-mosi-hs > pdmpdm-clk0m0 >pdm-clk0m1 >pdm-clk1 >pdm-sdi0m0 >pdm-sdi0m1 >pdm-sdi1 >pdm-sdi2 >pdm-sdi3 >pdm-clk0m0-sleep >pdm-clk0m1-sleep >pdm-clk1-sleep >pdm-sdi0m0-sleep >pdm-sdi0m1-sleep >pdm-sdi1-sleep >pdm-sdi2-sleep >pdm-sdi3-sleep >i2s0i2s0-8ch-mclk >i2s0-8ch-sclktx >!,i2s0-8ch-sclkrx > !-i2s0-8ch-lrcktx >!.i2s0-8ch-lrckrx > !/i2s0-8ch-sdo0 >!0i2s0-8ch-sdo1 >!2i2s0-8ch-sdo2 >!4i2s0-8ch-sdo3 >!6i2s0-8ch-sdi0 >!1i2s0-8ch-sdi1 > !3i2s0-8ch-sdi2 > !5i2s0-8ch-sdi3 >!7i2s1i2s1-2ch-mclk >i2s1-2ch-sclk >!8i2s1-2ch-lrck >!9i2s1-2ch-sdi >!:i2s1-2ch-sdo >!;i2s2i2s2-2ch-mclk >i2s2-2ch-sclk >!<i2s2-2ch-lrck >!=i2s2-2ch-sdi >!>i2s2-2ch-sdo >!?sdmmcsdmmc-clk >!vsdmmc-cmd >!wsdmmc-det >!xsdmmc-bus1 >sdmmc-bus4@ >!ysdiosdio-clk >!}sdio-cmd >!|sdio-bus4@ >!{emmcemmc-clk > !emmc-cmd > !emmc-rstnout > emmc-bus1 >emmc-bus4@ >emmc-bus8 >!emmc-reset > !flashflash-cs0 >!flash-rdy > !flash-dqs > !flash-ale > !flash-cle > !flash-wrn > !flash-csl >flash-rdn >!flash-bus8 >!sfcsfc-bus4@ >!sfc-bus2 >sfc-cs0 >!sfc-clk > !lcdclcdc-rgb-dclk-pin >lcdc-rgb-m0-hsync-pin >lcdc-rgb-m0-vsync-pin >lcdc-rgb-m0-den-pin >lcdc-rgb888-m0-data-pins >     lcdc-rgb666-m0-data-pins >     lcdc-rgb565-m0-data-pins >     lcdc-rgb888-m1-data-pins >   lcdc-rgb666-m1-data-pins >   lcdc-rgb565-m1-data-pins >   pwm0pwm0-pin >!dpwm1pwm1-pin >!epwm2pwm2-pin > !fpwm3pwm3-pin >!gpwm4pwm4-pin >!hpwm5pwm5-pin >!ipwm6pwm6-pin >!jpwm7pwm7-pin >!kgmacrmii-pins > !smac-refclk-12ma > !tmac-refclk > cif-m0cif-clkout-m0 > dvp-d2d9-m0 >   dvp-d0d1-m0 > d10-d11-m0 >cif-m1cif-clkout-m1 >dvp-d2d9-m1 >  dvp-d0d1-m1 >d10-d11-m1 >ispisp-prelight >pmicpmic_int >!Uledsblue-led > !green-led > !sdio-pwrseqwifi-enable-h >!emmc-pwrseqmmc-pwrseq-emmchZdefault L !vcc5v0-sys-regulatorregulator-fixed vcc5v0_sys;OLK@LK@ X!Vchosen cserial2:115200n8dc-12v-regulatorregulator-fixeddc_12v;O!adc-keys adc-keys o {buttons ` dbutton-recovery Recovery h FPleds gpio-ledsZdefaulthblue-led  on heartbeat R  px30-mb-jd4:blue:work heartbeatgreen-led  on power R  px30-mb-jd4:blue:diy default-onsdio-pwrseqmmc-pwrseq-simpleZdefaulth LT!~vcc5v0-baseboard-regulatorregulator-fixedvcc5v0_baseboard;OLK@LK@ X! compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1ethernet0mmc0mmc1mmc2device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfresetsreset-names#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,outputremote-endpointrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendnum-cs#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modeclock_in_outphy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplykeep-power-in-suspendnon-removablemmc-pwrseqmmc-hs200-1_8vmali-supplyiommus#iommu-cellsrockchip,disable-mmu-resetrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsreset-gpiosvin-supplystdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltcolordefault-statefunctionlinux,default-trigger