8( ,friendlyarm,nanopi-r2s-plusrockchip,rk3328 +7FriendlyElec NanoPi R2S Plusaliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000/ethernet@ff540000/usb@ff600000/device@2/mmc@ff500000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci@0=J@\iz cpu@1cpuarm,cortex-a53xpsci@0=J@\iz cpu@2cpuarm,cortex-a53xpsci@0=J@\iz cpu@3cpuarm,cortex-a53xpsci@0=J@\iz idle-statespscicpu-sleeparm,idle-statexl2-cachecache @2opp-table-0operating-points-v2opp-408000000Q ~.@?opp-600000000#F ~.@opp-8160000000, B@.@opp-1008000000< .@opp-1200000000G (.@opp-1296000000M?d  .@analog-soundsimple-audio-cardKi2sd~Analog disabledsimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg display-subsystemrockchip,display-subsystem  disabledhdmi-soundsimple-audio-cardKi2sd~HDMI disabledsimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24mEi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk   txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclk txrx disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclk txrx disabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk  tx&default4 disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclk rx&defaultsleep4> disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd:io-domains"rockchip,rk3328-io-voltage-domainokayHUcqgpiorockchip,rk3328-grf-gpiopower-controller!rockchip,rk3328-power-controller+<power-domain@6power-domain@5 BABpower-domain@8Freboot-modesyscon-reboot-modeRBRBRB  RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclk txrx&default 4 !"# disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclk txrx&default 4#$%# disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclk txrx&default4&#okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclk&default4' disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclk&default4(okaypmic@18rockchip,rk805 )xin32krk805-clkout24*&default-N\+h+t+++regulatorsDCDC_REG1vdd_log 4  0regulator-state-mem6B@DCDC_REG2vdd_arm 4  0regulator-state-mem6~DCDC_REG3vcc_ddrregulator-state-memDCDC_REG4 vcc_io_332Z2Zregulator-state-mem62ZLDO_REG1vcc_18w@w@regulator-state-mem6w@LDO_REG2 vcc18_emmcw@w@regulator-state-mem6w@LDO_REG3vdd_10B@B@regulator-state-mem6B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclk&default4, disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclk&default4- disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk  txrx&default4./01 disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclk&default42R disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclk&default43R disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclk&default44Rokaypwm@ff1b0030rockchip,rk3328-pwm0< pwmpclk&default45R disableddma-controller@ff1f0000arm,pl330arm,primecell@] apb_pclktthermal-zonessoc-thermal6tripstrip-point0ppassivetrip-point1Lpassive7soc-crits criticalcooling-mapsmap070 tsadc@ff250000rockchip,rk3328-tsadc% :$ P$tsadcapb_pclk&initdefaultsleep48>9"8,B 3tsadc-apb?:Lcokayy6efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1aFadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P%saradcapb_pclk,V 3saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 buscore,fiommu@ff330200rockchip,iommu3 ` aclkiface disablediommu@ff340800rockchip,iommu4@ bF aclkiface disabledvideo-codec@ff350000rockchip,rk3328-vpu5  vdpuF aclkhclk;<iommu@ff350800rockchip,iommu5@  F aclkiface<;video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6  BABaxiahbcabaccoreAB  ׄׄ=<iommu@ff360480rockchip,iommu 6@6@ JB aclkiface<=vop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop, 3axiahbdclk> disabledport+ endpoint@0?Diommu@ff373f00rockchip,iommu7?  ; aclkiface disabled>hdmi@ff3c0000rockchip,rk3328-dw-hdmi< #Fiahbisfrcec@hdmi&default 4ABC?: disabledports+port@0endpointD?port@1codec@ff410000rockchip,rk3328-codecA* pclkmclk?: disabledphy@ff430000rockchip,rk3328-hdmi-phyC SEysysclkrefoclkrefpclk hdmi_phy'F 3cpu-versionD disabled@clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD?:Ox=&'(ABDC"\5H4$\zEEE| n6n6n6ׄn6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyEphyclk usb480m_phy{\GokayGotg-portD$;<=otg-bvalidotg-idlinestateokayWhost-portD > linestateokayXmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-samples~р,m3resetokay4HIJK&defaultLmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-samples~р,n3reset disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-samples~р,o3resetokay!&default 4MNOethernet@ff540000rockchip,rk3328-gmacT macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac,c 3stmmaceth?:/=Kokaydf\PPVinputcQnrgmiiw4R&default$mdiosnps,dwmac-mdio+ethernet-phy@14S&default'P )Qethernet@ff550000rockchip,rk3328-gmacU?: macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy,b 3stmmacethnrmiicT/=KVoutput disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22V,d&default4UVTusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motghost @ W usb2-phyokayusb@ff5c0000 generic-ehci\  NGXusbokayusb@ff5d0000 generic-ohci]  NGXusbokaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc_@  @MQbiuciuciu-driveciu-samples~р,h3reset disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`aref_clksuspend_clkbus_clkhost utmi_wide  ? W y  okay+device@2 usbbda,8153interrupt-controller@ff811000 arm,gic-400  @ @ `   crypto@ff060000rockchip,rk3328-crypto@ PQ;hclk_masterhclk_slavesclk,D 3crypto-rstpinctrlrockchip,rk3328-pinctrl?:+ gpio@ff210000rockchip,gpio-bank! 3  egpio@ff220000rockchip,gpio-bank" 4  )gpio@ff230000rockchip,gpio-bank# 5  igpio@ff240000rockchip,gpio-bank$ 6  pcfg-pull-up [pcfg-pull-down cpcfg-pull-none Ypcfg-pull-none-2ma  "bpcfg-pull-up-2ma  "pcfg-pull-up-4ma  "\pcfg-pull-none-4ma  "_pcfg-pull-down-4ma  "pcfg-pull-none-8ma  "]pcfg-pull-up-8ma  "^pcfg-pull-none-12ma  " `pcfg-pull-up-12ma  " apcfg-output-high 1pcfg-output-low =pcfg-input-high  HZpcfg-input Hi2c0i2c0-xfer UYY'i2c1i2c1-xfer UYY(i2c2i2c2-xfer U YY,i2c3i2c3-xfer UYY-i2c3-pins UYYhdmi_i2chdmii2c-xfer UYYBpdm-0pdmm0-clk UYpdmm0-fsync UYpdmm0-sdi0 UYpdmm0-sdi1 UYpdmm0-sdi2 UYpdmm0-sdi3 UYpdmm0-clk-sleep UZpdmm0-sdi0-sleep UZpdmm0-sdi1-sleep UZpdmm0-sdi2-sleep UZpdmm0-sdi3-sleep UZpdmm0-fsync-sleep UZtsadcotp-pin U Y8otp-out U Y9uart0uart0-xfer U Y[ uart0-cts U Y!uart0-rts U Y"uart0-rts-pin U Yuart1uart1-xfer UY[#uart1-cts UY$uart1-rts UY%uart1-rts-pin UYuart2-0uart2m0-xfer UY[uart2-1uart2m1-xfer UY[&spi0-0spi0m0-clk U[spi0m0-cs0 U [spi0m0-tx U [spi0m0-rx U [spi0m0-cs1 U [spi0-1spi0m1-clk U[spi0m1-cs0 U[spi0m1-tx U[spi0m1-rx U[spi0m1-cs1 U[spi0-2spi0m2-clk U[.spi0m2-cs0 U[1spi0m2-tx U[/spi0m2-rx U[0i2s1i2s1-mclk UYi2s1-sclk UYi2s1-lrckrx UYi2s1-lrcktx UYi2s1-sdi UYi2s1-sdo UYi2s1-sdio1 UYi2s1-sdio2 UYi2s1-sdio3 UYi2s1-sleep UZZZZZZZZZi2s2-0i2s2m0-mclk UYi2s2m0-sclk UYi2s2m0-lrckrx UYi2s2m0-lrcktx UYi2s2m0-sdi UYi2s2m0-sdo UYi2s2m0-sleep` UZZZZZZi2s2-1i2s2m1-mclk UYi2s2m1-sclk UYi2sm1-lrckrx UYi2s2m1-lrcktx UYi2s2m1-sdi UYi2s2m1-sdo UYi2s2m1-sleepP UZZZZZspdif-0spdifm0-tx UYspdif-1spdifm1-tx UYspdif-2spdifm2-tx UYsdmmc0-0sdmmc0m0-pwren U\sdmmc0m0-pin U\sdmmc0-1sdmmc0m1-pwren U\sdmmc0m1-pin U\ksdmmc0sdmmc0-clk U]Hsdmmc0-cmd U^Isdmmc0-dectn U\Jsdmmc0-wrprt U\sdmmc0-bus1 U^sdmmc0-bus4@ U^^^^Ksdmmc0-pins U\\\\\\\\sdmmc0extsdmmc0ext-clk U_sdmmc0ext-cmd U\sdmmc0ext-wrprt U\sdmmc0ext-dectn U\sdmmc0ext-bus1 U\sdmmc0ext-bus4@ U\\\\sdmmc0ext-pins U\\\\\\\\sdmmc1sdmmc1-clk U ]sdmmc1-cmd U ^sdmmc1-pwren U^sdmmc1-wrprt U^sdmmc1-dectn U^sdmmc1-bus1 U^sdmmc1-bus4@ U^^^^sdmmc1-pins U \ \\\\\\\\emmcemmc-clk U`Memmc-cmd UaNemmc-pwren UYemmc-rstnout UYemmc-bus1 Uaemmc-bus4@ Uaaaaemmc-bus8 UaaaaaaaaOpwm0pwm0-pin UY2pwm1pwm1-pin UY3pwm2pwm2-pin UY4pwmirpwmir-pin UY5gmac-1rgmiim1-pins` U ] __]___ _ _] ]__]]] ]_]]]]Rrmiim1-pins Ub`bbbb b b` ` Y YYYYYgmac2phyfephyled-speed10 UYfephyled-duplex UYfephyled-rxm1 UYUfephyled-txm1 UYfephyled-linkm1 UYVtsadc_pintsadc-int U Ytsadc-pin U Yhdmi_pinhdmi-cec UYAhdmi-hpd UcCcif-0dvp-d2d9-m0 UYYYYY Y Y YYYYYcif-1dvp-d2d9-m1 UYYYYYYYYYYYYbuttonreset-button-pin UYdgmac2ioeth-phy-reset-pin UcSledslan-led-pin UYfsys-led-pin UYgwan-led-pin UYhlanlan-vdd-pin UYlpmicpmic-int-l U[*sdsdio-vcc-pin U[jchosen cserial2:1500000n8gmac-clock fixed-clocksY@ gmac_clkinPkeys gpio-keys4d&defaultkey-reset oreset e u 2leds gpio-leds 4fgh&defaultled-0 i onanopi-r2s:green:lanled-1 e onanopi-r2s:red:sys onled-2 i onanopi-r2s:green:wansdmmcio-regulatorregulator-gpio  )4j&default vcc_io_sdiow@2Z  voltage w@2Z sdmmc-regulatorregulator-fixed e4k&defaultvcc_sd2Z2Z Lvdd-5vregulator-fixedvdd_5vLK@LK@+vdd-5v-lanregulator-fixed  i4l&default vdd_5v_lan + compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-hs200-1_8vnon-removabletx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-handlephy-modephy-supplyrx_delaysnps,aaltx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervaldefault-stateenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio