R8D(4Dx"tsd,rk3588-jaguarrockchip,rk3588 +$7Theobroma Systems RK3588-SBC Jaguaraliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/ethernet@fe1b0000/mmc@fe2e0000/mmc@fe2c0000/i2c@fd880000/rtc@6fcpus+cpu-mapcluster0core0 core1 core2 core3 cluster1core0 core1 cluster2core0 core1 cpu@0cpuarm,cortex-a55psci,? F V0,k {@@  !,cpu@100cpuarm,cortex-a55psci,? k {@@ !,cpu@200cpuarm,cortex-a55psci,? k {@@ !,cpu@300cpuarm,cortex-a55psci,? k {@@ !,cpu@400cpuarm,cortex-a76psci,? F V0,k {@@ !,cpu@500cpuarm,cortex-a76psci,? k {@@ !,cpu@600cpuarm,cortex-a76psci,? F V0,k {@@ !,cpu@700cpuarm,cortex-a76psci,? k {@@ !, idle-states4pscicpu-sleeparm,idle-stateARidzx, l2-cache-l0cache}@, l2-cache-l1cache}@,l2-cache-l2cache}@,l2-cache-l3cache}@,l2-cache-b0cache}@,l2-cache-b1cache}@,l2-cache-b2cache}@,l2-cache-b3cache}@,l3-cachecache}0@,display-subsystemrockchip,display-subsystemfirmwareopteelinaro,optee-tz%smcscmi arm,scmi-smc+protocol@14, protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0%smcclock-0 fixed-clock)׫splltimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram$+sram@0arm,scmi-shmem,gpu@fb000000*rockchip,rk3588-maliarm,mali-valhall-csf F V ?+corecoregroupstacks 0\]^ jobmmugpu7 Eokay !L",usb@fc000000rockchip,rk3588-dwc3snps,dwc3@?+ref_clksuspend_clkbus_clkXotg `#$eusb2-phyusb3-phy outmi_wide7 xR  Edisabledusb@fc800000"rockchip,rk3588-ehcigeneric-ehci?%`&eusb7 Eokayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci?%`&eusb7 Eokayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci?'`(eusb7 Eokayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci?'`(eusb7 Eokayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(?jihkr&+ref_clksuspend_clkbus_clkutmipipeXhost`) eusb3-phy outmi_widex4 + Edisablediommu@fc900000 arm,smmu-v3 @qsvoeventqgerrorpriqcmdq-syncE Edisablediommu@fcb00000 arm,smmu-v3 @}{eventqgerrorpriqcmdq-syncE Edisabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdX,nsyscon@fd58c000rockchip,rk3588-sys-grfsysconX,isyscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ ,jsyscon@fd5a6000rockchip,rk3588-vo0-grfsysconZ` ?,syscon@fd5a8000rockchip,rk3588-vo1-grfsysconZ@?,ksyscon@fd5ac000rockchip,rk3588-usb-grfsysconZ@,syscon@fd5b0000rockchip,rk3588-php-grfsyscon[,+syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon[,syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@,syscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsyscon\@,syscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+,usb2phy@0rockchip,rk3588-usb2phy?+phyclk usb480m_phy0xmRphyapb Edisabled,otg-port^ Edisabled,#syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@8000rockchip,rk3588-usb2phy?+phyclk usb480m_phy2xoRphyapbEokay,%host-port^Eokayi*,&syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@c000rockchip,rk3588-usb2phy?+phyclk usb480m_phy3xp RphyapbEokay,'host-port^Eokay,(syscon@fd5e0000$rockchip,rk3588-hdptxphy-grfsyscon^,syscon@fd5f0000rockchip,rk3588-iocsyscon_,sram@fd600000 mmio-sram`$`+clock-controller@fd7c0000rockchip,rk3588-cru|F]q@VA.2Fq)׫ׄe/ׄ eZ р t+,i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=?ts +i2cpclk,default+Eokayfan@18 ti,amc6821regulator@42rockchip,rk8602B vdd_npu_s0dp~0-regulator-state-mem;regulator@43 rockchip,rk8603rockchip,rk8602Cvdd_cpu_big1_s0dp0-,regulator-state-mem;rtc@6f isil,isl1208oserial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK?+baudclkapb_pclkT..Ytxrx/defaultcmEokaypwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm? +pwmpclk0defaultz Edisabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm? +pwmpclk1defaultz Edisabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm ? +pwmpclk2defaultz Edisabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0? +pwmpclk3defaultz Edisabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfd,lpower-controller!rockchip,rk3588-power-controller+Eokay, power-domain@8+power-domain@9  ?!#" 456+power-domain@10 ?!#"7power-domain@11 ?!#"8power-domain@12 ?9:;<power-domain@13 +power-domain@14(?=power-domain@15 ?>power-domain@16? ?@A+power-domain@17 ? BCDpower-domain@21? EFGHIJKL+power-domain@23?CAMpower-domain@14 ?=power-domain@15?>power-domain@22?Npower-domain@24?[Z]OP+power-domain@258?ZQpower-domain@268?QRSpower-domain@270?TUVW+power-domain@28 ?XYpower-domain@29(?Z[power-domain@30?z{\power-domain@31@?W]^_`power-domain@33!?WZ[power-domain@34"?WZ[power-domain@37%?2apower-domain@38&?45power-domain@40(bvideo-codec@fdb50000+rockchip,rk3588-vpu121rockchip,rk3568-vpuwvdpu? +aclkhclkc7 iommu@fdb50800,rockchip,rk3588-iommurockchip,rk3568-iommu@v +aclkiface?7 E,crga@fdb80000(rockchip,rk3588-rgarockchip,rk3288-rgat?+aclkhclksclkxrqp Rcoreaxiahb7 video-codec@fdba0000rockchip,rk3588-vepu121z? +aclkhclkd7 iommu@fdba0800,rockchip,rk3588-iommurockchip,rk3568-iommu@y? +aclkiface7 E,dvideo-codec@fdba4000rockchip,rk3588-vepu121@|? +aclkhclke7 iommu@fdba4800,rockchip,rk3588-iommurockchip,rk3568-iommuH@{? +aclkiface7 E,evideo-codec@fdba8000rockchip,rk3588-vepu121~? +aclkhclkf7 iommu@fdba8800,rockchip,rk3588-iommurockchip,rk3568-iommu@}? +aclkiface7 E,fvideo-codec@fdbac000rockchip,rk3588-vepu121? +aclkhclkg7 iommu@fdbac800,rockchip,rk3588-iommurockchip,rk3568-iommu@? +aclkiface7 E,gvideo-codec@fdc70000rockchip,rk3588-av1-vpulvdpuFACVׄׄ?AC +aclkhclk7  xvop@fdd90000rockchip,rk3588-vop BPvopgamma-lut8?]\abcd[7+aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_voph7 tijkl Edisabledports+,port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~?]\ +aclkifaceE7  Edisabled,hi2s@fddc0000rockchip,rk3588-i2s-tdm?+mclk_txmclk_rxhclkFTmYtx7 xRtx-m Edisabledi2s@fddf0000rockchip,rk3588-i2s-tdm?445+mclk_txmclk_rxhclkF1TmYtx7 xRtx-m Edisabledi2s@fddfc000rockchip,rk3588-i2s-tdm?00,+mclk_txmclk_rxhclkF-TmYrx7 xRrx-m Edisabledqos@fdf35000rockchip,rk3588-qossysconP ,9qos@fdf35200rockchip,rk3588-qossysconR ,:qos@fdf35400rockchip,rk3588-qossysconT ,;qos@fdf35600rockchip,rk3588-qossysconV ,<qos@fdf36000rockchip,rk3588-qossyscon` ,\qos@fdf39000rockchip,rk3588-qossyscon ,aqos@fdf3d800rockchip,rk3588-qossyscon ,bqos@fdf3e000rockchip,rk3588-qossyscon ,^qos@fdf3e200rockchip,rk3588-qossyscon ,]qos@fdf3e400rockchip,rk3588-qossyscon ,_qos@fdf3e600rockchip,rk3588-qossyscon ,`qos@fdf40000rockchip,rk3588-qossyscon ,Zqos@fdf40200rockchip,rk3588-qossyscon ,[qos@fdf40400rockchip,rk3588-qossyscon ,Tqos@fdf40500rockchip,rk3588-qossyscon ,Uqos@fdf40600rockchip,rk3588-qossyscon ,Vqos@fdf40800rockchip,rk3588-qossyscon ,Wqos@fdf41000rockchip,rk3588-qossyscon ,Xqos@fdf41100rockchip,rk3588-qossyscon ,Yqos@fdf60000rockchip,rk3588-qossyscon ,?qos@fdf60200rockchip,rk3588-qossyscon ,@qos@fdf60400rockchip,rk3588-qossyscon ,Aqos@fdf61000rockchip,rk3588-qossyscon ,Bqos@fdf61200rockchip,rk3588-qossyscon ,Cqos@fdf61400rockchip,rk3588-qossyscon ,Dqos@fdf62000rockchip,rk3588-qossyscon ,=qos@fdf63000rockchip,rk3588-qossyscon0 ,>qos@fdf64000rockchip,rk3588-qossyscon@ ,Mqos@fdf66000rockchip,rk3588-qossyscon` ,Eqos@fdf66200rockchip,rk3588-qossysconb ,Fqos@fdf66400rockchip,rk3588-qossyscond ,Gqos@fdf66600rockchip,rk3588-qossysconf ,Hqos@fdf66800rockchip,rk3588-qossysconh ,Iqos@fdf66a00rockchip,rk3588-qossysconj ,Jqos@fdf66c00rockchip,rk3588-qossysconl ,Kqos@fdf66e00rockchip,rk3588-qossysconn ,Lqos@fdf67000rockchip,rk3588-qossysconp ,Nqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon ,7qos@fdf71000rockchip,rk3588-qossyscon ,8qos@fdf72000rockchip,rk3588-qossyscon ,4qos@fdf72200rockchip,rk3588-qossyscon" ,5qos@fdf72400rockchip,rk3588-qossyscon$ ,6qos@fdf80000rockchip,rk3588-qossyscon ,Qqos@fdf81000rockchip,rk3588-qossyscon ,Rqos@fdf81200rockchip,rk3588-qossyscon ,Sqos@fdf82000rockchip,rk3588-qossyscon ,Oqos@fdf82200rockchip,rk3588-qossyscon" ,Pdfi@fe060000rockchip,rk3588-dfi@&0:npcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0?CH>MR)+aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr#`6ooooDUd0p0l`) epcie-phy7 "T$ @ @0 @@dbiapbconfigx). Rpwrpipe+ Edisabledlegacy-interrupt-controllerv ,opcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O0?DI?NSs)+aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr#`6qqqqDUd@p@l`r epcie-phy7 "T$ @ @0 A@dbiapbconfigx*/ Rpwrpipe+ Edisabledlegacy-interrupt-controllerv ,qethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(?67Y^50+stmmacethclk_mac_refpclk_macaclk_macptp_ref7 !x$ Rstmmacethti+stu Edisabledmdiosnps,dwmac-mdio+stmmac-axi-config,srx-queues-config,tqueue0queue1tx-queues-config,,uqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci!(?b_eTo+satapmaliverxoobrefasicB+ Edisabledsata-port@0T@`r esata-phya p sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(?dagVq+satapmaliverxoobrefasicB+ Edisabledsata-port@0T@`) esata-phya p spi@fe2b0000 rockchip,sfc+@?/0+clk_sfchclk_sfc+ Edisabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ ?  +biuciuciu-driveciu-sampleрdefault vwx7 (Eokay yzmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ ?+biuciuciu-driveciu-sample default{7 % Edisabledmmc@fe2e0000rockchip,rk3588-dwcmshc.F-., V n6 (?,*+-.+corebusaxiblocktimer |}~default(xRcorebusaxiblocktimerEokay#5BQ`z yi2s@fe470000rockchip,rk3588-i2s-tdmG?+/(+mclk_txmclk_rxhclkF)-T..Ytxrx7 &x*+ Rtx-mrx-mdefault( Edisabledi2s@fe480000rockchip,rk3588-i2s-tdmH?y}u+mclk_txmclk_rxhclkT..Ytxrxx^_ Rtx-mrx-mdefault( Edisabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI?+i2s_clki2s_hclkFTYtxrx7 &default Edisabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ?%+i2s_clki2s_hclkF"TYtxrx7 &default Edisabledinterrupt-controller@fe600000 arm,gic-v3 `h va8$+,msi-controller@fe640000arm,gic-v3-itsd,pmsi-controller@fe660000arm,gic-v3-itsf,ppi-partitionsinterrupt-partition-0,interrupt-partition-1 ,dma-controller@fea10000arm,pl330arm,primecell@ VW ?n +apb_pclk ,.dma-controller@fea30000arm,pl330arm,primecell@ XY ?o +apb_pclk ,i2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c?{ +i2cpclk>default+ Edisabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c?| +i2cpclk?default+ Edisabledi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c?} +i2cpclk@default+ Edisabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c?~ +i2cpclkAdefault+ Edisabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c? +i2cpclkBdefault+ Edisabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !?TW +pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt?dc +tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF?+spiclkapb_pclkT..Ytxrx # default+ Edisabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG?+spiclkapb_pclkT..Ytxrx # default+ Edisabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH?+spiclkapb_pclkTYtxrx #default+EokayFV pmic@0rockchip,rk806  * :default FB@ X p- |- - - - - - - - -  -   -dvs1-null-pins )gpio_pwrctrl1 .pin_fun0,dvs2-null-pins )gpio_pwrctrl2 .pin_fun0,dvs3-null-pins )gpio_pwrctrl3 .pin_fun0,regulatorsdcdc-reg1dp~0 vdd_gpu_s0 7,"regulator-state-mem;dcdc-reg2vdd_cpu_lit_s0dp~0,regulator-state-mem;dcdc-reg3 vdd_log_s0 L q0regulator-state-mem; S qdcdc-reg4 vdd_vdenc_s0dp~0regulator-state-mem;dcdc-reg5 vdd_ddr_s0 L 0regulator-state-mem; S Pdcdc-reg6 vdd2_ddr_s3regulator-state-mem odcdc-reg7vdd_2v0_pldo_s30,regulator-state-mem o Sdcdc-reg8 vcc_3v3_s32Z2Z,yregulator-state-mem o S2Zdcdc-reg9 vddq_ddr_s0regulator-state-mem;dcdc-reg10 vcc_1v8_s3w@w@,regulator-state-mem o Sw@pldo-reg1 vcca_1v8_s0w@w@regulator-state-mem;pldo-reg2 vcc_1v8_s0w@w@,regulator-state-mem; Sw@pldo-reg3 vdda_1v2_s0OOregulator-state-mem;pldo-reg4 vcca_3v3_s02Z2Z0regulator-state-mem;pldo-reg5 vccio_sd_s0w@2Z0,zregulator-state-mem;pldo-reg6 pldo6_s3w@w@regulator-state-mem o Sw@nldo-reg1 vdd_0v75_s3 q qregulator-state-mem o S qnldo-reg2vdda_ddr_pll_s0 P Pregulator-state-mem; S Pnldo-reg3 vdda_0v75_s0 q qregulator-state-mem;nldo-reg4 vdda_0v85_s0 P Pregulator-state-mem;nldo-reg5 vdd_0v75_s0 q qregulator-state-mem;spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI?+spiclkapb_pclkTYtxrx # default+ Edisabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL?+baudclkapb_pclkT.. Ytxrxdefaultmc Edisabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM?+baudclkapb_pclkT. . YtxrxdefaultmcEokayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN?+baudclkapb_pclkT. . YtxrxdefaultmcEokay serial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO?+baudclkapb_pclkT Ytxrxdefaultmc Edisabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP?+baudclkapb_pclkT Ytxrxdefaultmc Edisabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ?+baudclkapb_pclkT Ytxrxdefaultmc Edisabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR?+baudclkapb_pclkTmmYtxrxdefaultmcEokayserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS?+baudclkapb_pclkTm m Ytxrxdefaultmc Edisabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT?+baudclkapb_pclkTm m Ytxrxdefaultmc Edisabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm?LK +pwmpclkdefaultz Edisabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm?LK +pwmpclkdefaultz Edisabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm ?LK +pwmpclkdefaultz Edisabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0?LK +pwmpclkdefaultz Edisabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm?ON +pwmpclkdefaultz Edisabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm?ON +pwmpclkdefaultz Edisabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm ?ON +pwmpclkdefaultz Edisabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0?ON +pwmpclkdefaultz Edisabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm?RQ +pwmpclkdefaultz Edisabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm?RQ +pwmpclkdefaultz Edisabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm ?RQ +pwmpclkdefaultz Edisabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0?RQ +pwmpclkdefaultz Edisabledthermal-zonespackage-thermal   tripspackage-crit 8  criticalbigcore0-thermal d  tripsbigcore0-alert L passive,bigcore0-crit 8  criticalcooling-mapsmap0  bigcore2-thermal d  tripsbigcore2-alert L passive,bigcore2-crit 8  criticalcooling-mapsmap0   littlecore-thermal d  tripslittlecore-alert L passive,littlecore-crit 8  criticalcooling-mapsmap0 0 center-thermal   tripscenter-crit 8  criticalgpu-thermal d  tripsgpu-alert L passive,gpu-crit 8  criticalcooling-mapsmap0  npu-thermal   tripsnpu-crit 8  criticaltsadc@fec00000rockchip,rk3588-tsadc?+tsadcapb_pclkFVxVWRtsadc-apbtsadc   5 P gpiootpout ZEokay,adc@fec10000rockchip,rk3588-saradc p?+saradcapb_pclkxU Rsaradc-apbEokay , i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c? +i2cpclkCdefault+ Edisabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c? +i2cpclkDdefault+Eokayeeprom@54st,24c04atmel,24c04T  yi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c? +i2cpclkEdefault+Eokayregulator@42rockchip,rk8602Bvdd_cpu_big0_s0dp0-,regulator-state-mem;spi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ?+spiclkapb_pclkTm mYtxrx # default+ Edisabledefuse@fecc0000rockchip,rk3588-otp ?+otpapb_pclkphyarbx Rotpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[ ?p +apb_pclk ,mphy@fed60000rockchip,rk3588-hdptx-phy ?T+refapb^8x#cde!""Rphyapbinitcmnlaneroplllcpllt Edisabledphy@fed80000rockchip,rk3588-usbdp-phy^?lV+refclkimmortalpclkutmi(x   Rinitcmnlanepcs_apbpma_apb     Edisabled,$phy@fee00000rockchip,rk3588-naneng-combphy?vW +refapbpipeFV^x<CRphyapb +  Edisabled,rphy@fee20000rockchip,rk3588-naneng-combphy?xW +refapbpipeFV^x>ERphyapb +  Edisabled,)sram@ff001000 mmio-sram$+pinctrlrockchip,rk3588-pinctrl$t+,gpio@fd8a0000rockchip,gpio-bank?qr *  v :,gpio@fec20000rockchip,gpio-bank?st *  v :,mdot2e-w-disable1-n-hog %  + 6m.2 E-key W_DISABLE1# @gpio@fec30000rockchip,gpio-bank?uv * @ v :, gpio@fec40000rockchip,gpio-bank?wx * ` v :gpio@fec50000rockchip,gpio-bank?yz *  v :,mdot2e-w-disable2-n-hog % + 6m.2 E-key W_DISABLE2# @pcfg-pull-up I,pcfg-pull-down V,pcfg-pull-none e,pcfg-pull-none-drv-level-2 e r,pcfg-pull-up-drv-level-1 I r,pcfg-pull-up-drv-level-2 I r,pcfg-pull-none-smt e ,auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-bus8 ,|emmc-clk ,~emmc-cmd ,}emmc-data-strobe ,emmc-reset , eth1fspigmac1gpuhdmii2c0i2c0m2-xfer ,,i2c1i2c1m4-xfer   ,i2c2i2c2m0-xfer   ,i2c3i2c3m0-xfer   ,i2c4i2c4m0-xfer   ,i2c5i2c5m0-xfer   ,i2c6i2c6m4-xfer   ,i2c7i2c7m0-xfer   ,i2c8i2c8m2-xfer   ,i2s0i2s0-lrck ,i2s0-sclk ,i2s0-sdi0 ,i2s0-sdi1 ,i2s0-sdi2 ,i2s0-sdi3 ,i2s0-sdo0 ,i2s0-sdo1 ,i2s0-sdo2 ,i2s0-sdo3 ,i2s1i2s1m0-lrck ,i2s1m0-sclk ,i2s1m0-sdi0 ,i2s1m0-sdi1 ,i2s1m0-sdi2 ,i2s1m0-sdi3 ,i2s1m0-sdo0  ,i2s1m0-sdo1  ,i2s1m0-sdo2  ,i2s1m0-sdo3  ,i2s2i2s2m1-lrck ,i2s2m1-sclk  ,i2s2m1-sdi  ,i2s2m1-sdo  ,i2s3i2s3-lrck ,i2s3-sclk ,i2s3-sdi ,i2s3-sdo ,jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pcie30x4-clkreqn-m0 ,pcie30x4-perstn-m0 ,pcie30x4-waken-m0  ,pdm0pdm1pmicpmic-pinsp ,pmupwm0pwm0m0-pins ,0pwm1pwm1m0-pins ,1pwm2pwm2m0-pins ,2pwm3pwm3m0-pins ,3pwm4pwm4m0-pins  ,pwm5pwm5m0-pins ,pwm6pwm6m0-pins  ,pwm7pwm7m0-pins  ,pwm8pwm8m0-pins  ,pwm9pwm9m0-pins  ,pwm10pwm10m0-pins  ,pwm11pwm11m0-pins  ,pwm12pwm12m0-pins  ,pwm13pwm13m0-pins  ,pwm14pwm14m0-pins  ,pwm15pwm15m0-pins  ,refclksatasata0sata1sata2sdiosdiom1-pins` ,{sdmmcsdmmc-bus4@ ,vsdmmc-clk ,xsdmmc-cmd ,wspdif0spdif1spi0spi0m0-pins0 ,spi0m0-cs0 ,spi0m0-cs1 ,spi1spi1m1-pins0 ,spi1m1-cs0 ,spi1m1-cs1 ,spi2spi2m2-pins0  ,spi2m2-cs0 ,spi3spi3m1-pins0  ,spi3m1-cs0 ,spi3m1-cs1 ,spi4spi4m0-pins0 ,spi4m0-cs0 ,spi4m0-cs1 ,tsadctsadc-shut ,uart0uart0m0-xfer ,/uart1uart1m1-xfer   ,uart2uart2m0-xfer  ,uart3uart3m2-xfer   ,uart3-rtsn  ,uart4uart4m1-xfer   ,uart5uart5m1-xfer   ,uart6uart6m1-xfer   ,uart7uart7m0-xfer   ,uart8uart8m1-xfer   ,uart9uart9m1-xfer   ,vopbt656gpio-functsadc-gpio-func ,eth0eth0-pins ,gmac0gmac0-miim ,gmac0-rx-bus20 ,gmac0-tx-bus20 ,gmac0-rgmii-clk  ,gmac0-rgmii-bus@   ,etherneteth-reset ,ledsled1-pin , usb@fc400000rockchip,rk3588-dwc3snps,dwc3@@?+ref_clksuspend_clkbus_clkXotg `eusb2-phyusb3-phy outmi_wide7 xS  Edisabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon[, syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon\,syscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon\@,syscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@@+,usb2phy@4000rockchip,rk3588-usb2phy@?+phyclk usb480m_phy1xnRphyapb Edisabled,otg-port^ Edisabled,i2s@fddc8000rockchip,rk3588-i2s-tdm܀?+mclk_txmclk_rxhclkFTmYtx7 xRtx-m Edisabledi2s@fddf4000rockchip,rk3588-i2s-tdm@?99?+mclk_txmclk_rxhclkF6TmYtx7 xRtx-m Edisabledi2s@fddf8000rockchip,rk3588-i2s-tdm߀?++'+mclk_txmclk_rxhclkF(TmYrx7 xRrx-m Edisabledi2s@fde00000rockchip,rk3588-i2s-tdm?&&"+mclk_txmclk_rxhclkF#TmYrx7 xRrx-m Edisabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+4?@E;JOt-+aclk_mstaclk_slvaclk_dbipclkauxpiperefpciPsyspmcmsglegacyerr#`6DUdl` epcie-phy7 "T$ @ @0 @@dbiapbconfigx&+ RpwrpipeEokaydefault  legacy-interrupt-controllerv ,pcie-ep@fe150000rockchip,rk3588-pcie-epP @ @ @ @0dbidbi2apbaddr_spaceatu0?@E;JOt)+aclk_mstaclk_slvaclk_dbipclkauxpipe +syspmcmsglegacyerrdma0dma1dma2dma3Ul` epcie-phy7 "x&+ Rpwrpipe Edisabledpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+0?AF<KPu)+aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr#`6DUdl` epcie-phy7 "T$ @ @@0 @@@dbiapbconfigx', Rpwrpipe Edisabledlegacy-interrupt-controllerv ,pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /0?BG=LQ)+aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr#`6DUd p l` epcie-phy7 "T$ @ @0 @@dbiapbconfigx(- Rpwrpipe+Eokay  legacy-interrupt-controllerv ,ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(?67X]40+stmmacethclk_mac_refpclk_macaclk_macptp_ref7 !x# Rstmmacethti+Eokay output  rgmiiidefault     'mdiosnps,dwmac-mdio+ethernet-phy@6ethernet-phy-ieee802.3-c22?,stmmac-axi-config,rx-queues-config,queue0queue1tx-queues-config,,queue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci"(?c`fUp+satapmaliverxoobrefasicB+ Edisabledsata-port@0T@` esata-phya p phy@fed90000rockchip,rk3588-usbdp-phy^?mW+refclkimmortalpclkutmi(xRinitcmnlanepcs_apbpma_apb     Edisabled,phy@fee10000rockchip,rk3588-naneng-combphy?wW +refapbpipeFV^x=DRphyapb + Eokay,phy@fee80000rockchip,rk3588-pcie3-phy^?y+pclkxHRphy + . Eokay,opp-table-cluster0operating-points-v2 ?, opp-1008000000 J< Q L L~ _@opp-1200000000 JG Q 4 4~ _@opp-1416000000 JTfr Q ~ _@ popp-1608000000 J_" Q P P~ _@opp-1800000000 JkI Q~~~ _@opp-table-cluster1operating-points-v2 ?,opp-1200000000 JG Q L LB@ _@opp-1416000000 JTfr Q  B@ _@opp-1608000000 J_" Q B@ _@opp-1800000000 JkI Q P PB@ _@opp-2016000000 Jx) QHHB@ _@opp-2208000000 Jh QllB@ _@opp-2400000000 J  QB@B@B@ _@opp-table-cluster2operating-points-v2 ?,opp-1200000000 JG Q L LB@ _@opp-1416000000 JTfr Q  B@ _@opp-1608000000 J_" Q B@ _@opp-1800000000 JkI Q P PB@ _@opp-2016000000 Jx) QHHB@ _@opp-2208000000 Jh QllB@ _@opp-2400000000 J  QB@B@B@ _@opp-tableoperating-points-v2,!opp-300000000 J Q L L Popp-400000000 Jׄ Q L L Popp-500000000 Je Q L L Popp-600000000 J#F Q L L Popp-700000000 J)' Q ` ` Popp-800000000 J/ Q q q Popp-900000000 J5 Q 5 5 Popp-1000000000 J; Q P P Padc-keys adc-keys |  buttons w@ dbutton-bios-disable BIOS_DISABLE h chosen serial2:115200n8dc-12v-regulatorregulator-fixeddc_12v,emmc-pwrseqmmc-pwrseq-emmc default  ,leds gpio-ledsdefault led-1 % .heartbeat heartbeatpcie-refclk-gen-clock fixed-clock,pcie-refclk-clockgpio-gate-clock? default,pps pps-gpio %vcc-1v1-nldo-s3-regulatorregulator-fixedvcc_1v1_nldo_s30-,vcc-1v2-s3-regulatorregulator-fixed vcc_1v2_s3OO0-,vcc-2v8-s3-regulatorregulator-fixed vcc_2v8_s3**0yvcc-5v0-usb-a-regulatorregulator-fixed usb_a_vccLK@LK@0-  !,*vcc-5v0-usb-c1-regulatorregulator-fixed 5v_usbc1LK@LK@0 !vcc-5v0-usb-c2-regulatorregulator-fixed 5v_usbc2LK@LK@0 !vcc3v3-mdot2-regulatorregulator-fixed vcc3v3_mdot22Z2Z0,vcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@0,-vcc5v0-usb-regulatorregulator-fixed vcc5v0_usbLK@LK@0-, compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4ethernet0mmc0mmc1rtc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namespower-domainsstatusmali-supplydr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosiommusreg-namesrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybroken-cdbus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-ddr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-ddr-1_8vmmc-hs200-1_8vmmc-hs400-1_8vmmc-hs400-enhanced-strobemmc-pwrseqno-sdiono-sdnon-removablesupports-cqerockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csgpio-controller#gpio-cellsspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplypinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendlinux,rs485-enabled-at-boot-timepolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplypagesizevcc-supplybitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesgpiosoutput-lowline-namegpio-hogbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsreset-gpiosvpcie3v3-supplyclock_in_outphy-handlephy-modetx_delayrx_delaysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usrockchip,phy-grfopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltstdout-pathlinux,default-triggercolorenable-gpiosenable-active-high