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1okayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci+&@'Eusb# 1okayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(+jihkr&ref_clksuspend_clkbus_clkutmipipe8host@( Eusb3-phy Outmi_wideX4_  1disablediommu@fc900000 arm,smmu-v3 @qsvoeventqgerrorpriqcmdq-sync% 1disablediommu@fcb00000 arm,smmu-v3 @}{eventqgerrorpriqcmdq-sync% 1disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdXmsyscon@fd58c000rockchip,rk3588-sys-grfsysconXhsyscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ isyscon@fd5a6000rockchip,rk3588-vo0-grfsysconZ` +syscon@fd5a8000rockchip,rk3588-vo1-grfsysconZ@+jsyscon@fd5ac000rockchip,rk3588-usb-grfsysconZ@syscon@fd5b0000rockchip,rk3588-php-grfsyscon[*syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon[syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@syscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsyscon\@syscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@0rockchip,rk3588-usb2phy+phyclk usb480m_phy0Xm2phyapb 1disabledotg-port> 1disabled"syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@8000rockchip,rk3588-usb2phy+phyclk usb480m_phy2Xo2phyapb1okay$host-port>1okayI)%syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@c000rockchip,rk3588-usb2phy+phyclk usb480m_phy3Xp 2phyapb1okay&host-port>1okayI)'syscon@fd5e0000$rockchip,rk3588-hdptxphy-grfsyscon^syscon@fd5f0000rockchip,rk3588-iocsyscon_sram@fd600000 mmio-sram``+clock-controller@fd7c0000rockchip,rk3588-cru|2]q@BA.2Fq)׫ׄe/ׄ eZ р T*i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=+ts i2cpclka+kdefault+1okayregulator@42rockchip,rk8602Byvdd_cpu_big0_s0dp,regulator-state-memregulator@43 rockchip,rk8603rockchip,rk8602Cyvdd_cpu_big1_s0dp,regulator-state-memserial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK+baudclkapb_pclk4--9txrxa.kdefaultCM 1disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+ pwmpclka/kdefaultZ 1disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+ pwmpclka0kdefaultZ 1disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm + pwmpclka1kdefaultZ1okaypwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+ pwmpclka2kdefaultZ 1disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfdkpower-controller!rockchip,rk3588-power-controllere+1okay power-domain@8e+power-domain@9  +!#" y345e+power-domain@10 +!#"y6epower-domain@11 +!#"y7epower-domain@12 +y89:;epower-domain@13 +epower-domain@14(+y<epower-domain@15 +y=epower-domain@16+ y>?@+epower-domain@17 + yABCepower-domain@21+ yDEFGHIJK+epower-domain@23+CAyLepower-domain@14 +y<epower-domain@15+y=epower-domain@22+yMepower-domain@24+[Z]yNO+epower-domain@258+ZyPepower-domain@268+QyQRepower-domain@270+ySTUV+epower-domain@28 +yWXepower-domain@29(+yYZepower-domain@30+z{y[epower-domain@31@+Wy\]^_epower-domain@33!+WZ[epower-domain@34"+WZ[epower-domain@37%+2y`epower-domain@38&+45epower-domain@40(yaevideo-codec@fdb50000+rockchip,rk3588-vpu121rockchip,rk3568-vpuwvdpu+ aclkhclkb# iommu@fdb50800,rockchip,rk3588-iommurockchip,rk3568-iommu@v aclkiface+# %brga@fdb80000(rockchip,rk3588-rgarockchip,rk3288-rgat+aclkhclksclkXrqp 2coreaxiahb# video-codec@fdba0000rockchip,rk3588-vepu121z+ aclkhclkc# iommu@fdba0800,rockchip,rk3588-iommurockchip,rk3568-iommu@y+ aclkiface# %cvideo-codec@fdba4000rockchip,rk3588-vepu121@|+ aclkhclkd# iommu@fdba4800,rockchip,rk3588-iommurockchip,rk3568-iommuH@{+ aclkiface# %dvideo-codec@fdba8000rockchip,rk3588-vepu121~+ aclkhclke# iommu@fdba8800,rockchip,rk3588-iommurockchip,rk3568-iommu@}+ aclkiface# %evideo-codec@fdbac000rockchip,rk3588-vepu121+ aclkhclkf# iommu@fdbac800,rockchip,rk3588-iommurockchip,rk3568-iommu@+ aclkiface# %fvideo-codec@fdc70000rockchip,rk3588-av1-vpulvdpu2ACBׄׄ+AC aclkhclk#  Xvop@fdd90000rockchip,rk3588-vop BPvopgamma-lut8+]\abcd[7aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vopg# Thijk 1disabledports+port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~+]\ aclkiface%#  1disabledgi2s@fddc0000rockchip,rk3588-i2s-tdm+mclk_txmclk_rxhclk24l9tx# X2tx-m 1disabledi2s@fddf0000rockchip,rk3588-i2s-tdm+445mclk_txmclk_rxhclk214l9tx# X2tx-m 1disabledi2s@fddfc000rockchip,rk3588-i2s-tdm+00,mclk_txmclk_rxhclk2-4l9rx# X2rx-m 1disabledqos@fdf35000rockchip,rk3588-qossysconP 8qos@fdf35200rockchip,rk3588-qossysconR 9qos@fdf35400rockchip,rk3588-qossysconT :qos@fdf35600rockchip,rk3588-qossysconV ;qos@fdf36000rockchip,rk3588-qossyscon` [qos@fdf39000rockchip,rk3588-qossyscon `qos@fdf3d800rockchip,rk3588-qossyscon aqos@fdf3e000rockchip,rk3588-qossyscon ]qos@fdf3e200rockchip,rk3588-qossyscon \qos@fdf3e400rockchip,rk3588-qossyscon ^qos@fdf3e600rockchip,rk3588-qossyscon _qos@fdf40000rockchip,rk3588-qossyscon Yqos@fdf40200rockchip,rk3588-qossyscon Zqos@fdf40400rockchip,rk3588-qossyscon Sqos@fdf40500rockchip,rk3588-qossyscon Tqos@fdf40600rockchip,rk3588-qossyscon Uqos@fdf40800rockchip,rk3588-qossyscon Vqos@fdf41000rockchip,rk3588-qossyscon Wqos@fdf41100rockchip,rk3588-qossyscon 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1disabledsata-port@04@@q Esata-phyA P sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(+dagVqsatapmaliverxoobrefasic"+ 1disabledsata-port@04@@( Esata-phyA P spi@fe2b0000 rockchip,sfc+@+/0clk_sfchclk_sfc+ 1disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ +  biuciuciu-driveciu-sample_j kdefaultauvwx# ( 1disabledmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ +biuciuciu-driveciu-sample_j kdefaultay# % 1disabledmmc@fe2e0000rockchip,rk3588-dwcmshc.2-., B n6 (+,*+-.corebusaxiblocktimerj az{|}~kdefault(X2corebusaxiblocktimer1okayxi2s@fe470000rockchip,rk3588-i2s-tdmG++/(mclk_txmclk_rxhclk2)-4--9txrx# &X*+ 2tx-mrx-mkdefault(a 1disabledi2s@fe480000rockchip,rk3588-i2s-tdmH+y}umclk_txmclk_rxhclk4--9txrxX^_ 2tx-mrx-mkdefault(a 1disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI+i2s_clki2s_hclk249txrx# &kdefaulta 1disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ+%i2s_clki2s_hclk2"49txrx# &kdefaulta 1disabledinterrupt-controller@fe600000 arm,gic-v3 `h Va8+msi-controller@fe640000arm,gic-v3-itsdomsi-controller@fe660000arm,gic-v3-itsfppi-partitionsinterrupt-partition-0interrupt-partition-1 dma-controller@fea10000arm,pl330arm,primecell@ VW+n apb_pclk1-dma-controller@fea30000arm,pl330arm,primecell@ XY+o apb_pclk1i2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c+{ i2cpclk>akdefault+ 1disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c+| i2cpclk?akdefault+1okayrtc@51haoyu,hym8563Qhym8563 kdefaulta<i2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c+} i2cpclk@akdefault+ 1disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c+~ i2cpclkAakdefault+ 1disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkBakdefault+ 1disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !+TW pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt+dc tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF+spiclkapb_pclk4--9txrxJ akdefault+ 1disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG+spiclkapb_pclk4--9txrxJ akdefault+ 1disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH+spiclkapb_pclk49txrxJakdefault+1okay2B pmic@0rockchip,rk806Qa kdefaultamB@,,,,,,,,, ,  , * 7 D,dvs1-null-pins Pgpio_pwrctrl1 Upin_fun0dvs2-null-pins Pgpio_pwrctrl2 Upin_fun0dvs3-null-pins Pgpio_pwrctrl3 Upin_fun0regulatorsdcdc-reg1 vdd_gpu_s0 ^dp~0regulator-state-memdcdc-reg2vdd_cpu_lit_s0dp~0regulator-state-memdcdc-reg3 vdd_log_s0 L q0regulator-state-mem z qdcdc-reg4 vdd_vdenc_s0dp~0regulator-state-memdcdc-reg5 vdd_ddr_s0 L 0regulator-state-mem z Pdcdc-reg6 vdd2_ddr_s3regulator-state-mem dcdc-reg7vdd_2v0_pldo_s3regulator-state-mem  zdcdc-reg8 vcc_3v3_s32Z2Zregulator-state-mem  z2Zdcdc-reg9 vddq_ddr_s0regulator-state-memdcdc-reg10 vcc_1v8_s3w@w@regulator-state-mem  zw@pldo-reg1 avcc_1v8_s0w@w@regulator-state-mempldo-reg2 vcc_1v8_s0w@w@regulator-state-mem zw@pldo-reg3 avdd_1v2_s0OOregulator-state-mempldo-reg4 vcc_3v3_s02Z2Zregulator-state-mempldo-reg5 vccio_sd_s0w@2Zregulator-state-mempldo-reg6 pldo6_s3w@w@regulator-state-mem  zw@nldo-reg1 vdd_0v75_s3 q qregulator-state-mem  z qnldo-reg2vdd_ddr_pll_s0 P Pregulator-state-mem z Pnldo-reg3 avdd_0v75_s0 | |regulator-state-memnldo-reg4 vdd_0v85_s0 P Pregulator-state-memnldo-reg5 vdd_0v75_s0 q qregulator-state-memspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI+spiclkapb_pclk49txrxJ akdefault+ 1disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL+baudclkapb_pclk4-- 9txrxakdefaultMC 1disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM+baudclkapb_pclk4- - 9txrxakdefaultMC1okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN+baudclkapb_pclk4- - 9txrxakdefaultMC 1disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO+baudclkapb_pclk4 9txrxakdefaultMC 1disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP+baudclkapb_pclk4 9txrxakdefaultMC 1disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ+baudclkapb_pclk4 9txrxakdefaultMC 1disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR+baudclkapb_pclk4ll9txrxakdefaultMC 1disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS+baudclkapb_pclk4l l 9txrxakdefaultMC 1disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT+baudclkapb_pclk4l l 9txrxakdefaultMC 1disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+LK pwmpclkakdefaultZ 1disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+LK pwmpclkakdefaultZ 1disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +LK pwmpclkakdefaultZ 1disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+LK pwmpclkakdefaultZ 1disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+ON pwmpclkakdefaultZ 1disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+ON pwmpclkakdefaultZ 1disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +ON pwmpclkakdefaultZ 1disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+ON pwmpclkakdefaultZ 1disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+RQ pwmpclkakdefaultZ 1disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+RQ pwmpclkakdefaultZ 1disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +RQ pwmpclkakdefaultZ 1disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+RQ pwmpclkakdefaultZ 1disabledthermal-zonespackage-thermal   tripspackage-crit 8  criticalbigcore0-thermal d  tripsbigcore0-alert L passivebigcore0-crit 8  criticalcooling-mapsmap0  bigcore2-thermal d  tripsbigcore2-alert L passivebigcore2-crit 8  criticalcooling-mapsmap0   littlecore-thermal d  tripslittlecore-alert L passivelittlecore-crit 8  criticalcooling-mapsmap0 0 center-thermal   tripscenter-crit 8  criticalgpu-thermal d  tripsgpu-alert L passivegpu-crit 8  criticalcooling-mapsmap0  npu-thermal   tripsnpu-crit 8  criticaltsadc@fec00000rockchip,rk3588-tsadc+tsadcapb_pclk2BXVW2tsadc-apbtsadc  $ ;a V kgpiootpout `1okayadc@fec10000rockchip,rk3588-saradc v+saradcapb_pclkXU 2saradc-apb1okay i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkCakdefault+ 1disabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkDakdefault+ 1disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkEakdefault+ 1disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ+spiclkapb_pclk4l l9txrxJ akdefault+ 1disabledefuse@fecc0000rockchip,rk3588-otp +otpapb_pclkphyarbX 2otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[+p apb_pclk1lphy@fed60000rockchip,rk3588-hdptx-phy +Trefapb>8X#cde!""2phyapbinitcmnlaneroplllcpllT 1disabledphy@fed80000rockchip,rk3588-usbdp-phy>+lVrefclkimmortalpclkutmi(X   2initcmnlanepcs_apbpma_apb     1disabled#phy@fee00000rockchip,rk3588-naneng-combphy+vW refapbpipe2B>X<C2phyapb * 1okayqphy@fee20000rockchip,rk3588-naneng-combphy+xW refapbpipe2B>X>E2phyapb * 1okay(sram@ff001000 mmio-sram+pinctrlrockchip,rk3588-pinctrlT+gpio@fd8a0000rockchip,gpio-bank+qrQ Vagpio@fec20000rockchip,gpio-bank+stQ Vagpio@fec30000rockchip,gpio-bank+uvQ @ Vagpio@fec40000rockchip,gpio-bank+wxQ ` Vagpio@fec50000rockchip,gpio-bank+yzQ Vapcfg-pull-up pcfg-pull-down $pcfg-pull-none 3pcfg-pull-none-drv-level-2 3 @pcfg-pull-up-drv-level-1  @pcfg-pull-up-drv-level-2  @pcfg-pull-none-smt 3 Oauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout dzemmc-bus8 d{emmc-clk d|emmc-cmd d}emmc-data-strobe d~eth1fspigmac1gpuhdmii2c0i2c0m2-xfer d+i2c1i2c1m0-xfer d  i2c2i2c2m0-xfer d  i2c3i2c3m0-xfer d  i2c4i2c4m0-xfer d  i2c5i2c5m0-xfer d  i2c6i2c6m0-xfer d  i2c7i2c7m0-xfer d  i2c8i2c8m0-xfer d  i2s0i2s0-lrck di2s0-sclk di2s0-sdi0 di2s0-sdi1 di2s0-sdi2 di2s0-sdi3 di2s0-sdo0 di2s0-sdo1 di2s0-sdo2 di2s0-sdo3 di2s1i2s1m0-lrck di2s1m0-sclk di2s1m0-sdi0 di2s1m0-sdi1 di2s1m0-sdi2 di2s1m0-sdi3 di2s1m0-sdo0 d i2s1m0-sdo1 d i2s1m0-sdo2 d i2s1m0-sdo3 d i2s2i2s2m1-lrck di2s2m1-sclk d i2s2m1-sdi d i2s2m1-sdo d i2s3i2s3-lrck di2s3-sclk di2s3-sdi di2s3-sdo djtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp dpmupwm0pwm0m0-pins d/pwm1pwm1m0-pins d0pwm2pwm2m0-pins d1pwm3pwm3m0-pins d2pwm4pwm4m0-pins d pwm5pwm5m0-pins d pwm6pwm6m0-pins d pwm7pwm7m0-pins d pwm8pwm8m0-pins d pwm9pwm9m0-pins d pwm10pwm10m0-pins d pwm11pwm11m0-pins d pwm12pwm12m0-pins d pwm13pwm13m0-pins d pwm14pwm14m0-pins d pwm15pwm15m0-pins d refclksatasata0sata1sata2sdiosdiom1-pins` dysdmmcsdmmc-bus4@ dxsdmmc-clk dusdmmc-cmd dvsdmmc-det dwspdif0spdif1spi0spi0m0-pins0 dspi0m0-cs0 dspi0m0-cs1 dspi1spi1m1-pins0 dspi1m1-cs0 dspi1m1-cs1 dspi2spi2m2-pins0 d spi2m2-cs0 d spi3spi3m1-pins0 d spi3m1-cs0 dspi3m1-cs1 dspi4spi4m0-pins0 dspi4m0-cs0 dspi4m0-cs1 dtsadctsadc-shut duart0uart0m1-xfer d .uart1uart1m1-xfer d  uart2uart2m0-xfer d uart3uart3m1-xfer d  uart4uart4m1-xfer d  uart5uart5m1-xfer d  uart6uart6m1-xfer d  uart7uart7m1-xfer d  uart8uart8m1-xfer d  uart9uart9m1-xfer d  vopbt656gpio-functsadc-gpio-func deth0gmac0gmac0-miim dgmac0-rx-bus20 dgmac0-tx-bus20 dgmac0-rgmii-clk d gmac0-rgmii-bus@ d  rtl8211frtl8211f-rst d hym8563hym8563-int dusbvcc5v0-host-en dusb@fc400000rockchip,rk3588-dwc3snps,dwc3@@+ref_clksuspend_clkbus_clk8otg @Eusb2-phyusb3-phy Outmi_wide# XS_ 1disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon[syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon\syscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon\@syscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@@+usb2phy@4000rockchip,rk3588-usb2phy@+phyclk usb480m_phy1Xn2phyapb 1disabledotg-port> 1disabledi2s@fddc8000rockchip,rk3588-i2s-tdm܀+mclk_txmclk_rxhclk24l9tx# X2tx-m 1disabledi2s@fddf4000rockchip,rk3588-i2s-tdm@+99?mclk_txmclk_rxhclk264l9tx# X2tx-m 1disabledi2s@fddf8000rockchip,rk3588-i2s-tdm߀+++'mclk_txmclk_rxhclk2(4l9rx# X2rx-m 1disabledi2s@fde00000rockchip,rk3588-i2s-tdm+&&"mclk_txmclk_rxhclk2#4l9rx# X2rx-m 1disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`$5DL@ Epcie-phy# "T @ @0 @@dbiapbconfigX&+ 2pwrpipe 1disabledlegacy-interrupt-controllerV pcie-ep@fe150000rockchip,rk3588-pcie-epP @ @ @ @0dbidbi2apbaddr_spaceatu0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipe +syspmcmsglegacyerrdma0dma1dma2dma35L@ Epcie-phy# "X&+ 2pwrpipe 1disabledpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+0+AF<KPu)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`$5DL@ Epcie-phy# "T @ @@0 @@@dbiapbconfigX', 2pwrpipe 1disabledlegacy-interrupt-controllerV pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /0+BG=LQ)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`$5D o L@ Epcie-phy# "T @ @0 @@dbiapbconfigX(- 2pwrpipe+ 1disabledlegacy-interrupt-controllerV ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(+67X]40stmmacethclk_mac_refpclk_macaclk_macptp_ref# !X# 2stmmacethThk*|1okay routput  rgmii-rxidakdefault  Cmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916kdefaulta N   stmmac-axi-configrx-queues-configqueue0queue1tx-queues-config queue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci"(+c`fUpsatapmaliverxoobrefasic"+ 1disabledsata-port@04@@ Esata-phyA P phy@fed90000rockchip,rk3588-usbdp-phy>+mWrefclkimmortalpclkutmi(X2initcmnlanepcs_apbpma_apb     1disabledphy@fee10000rockchip,rk3588-naneng-combphy+wW refapbpipe2B>X=D2phyapb *  1disabledphy@fee80000rockchip,rk3588-pcie3-phy>+ypclkXH2phy *  1disabledopp-table-cluster0operating-points-v2  opp-1008000000 < L L~ @opp-1200000000 G 4 4~ @opp-1416000000 Tfr ~ @ opp-1608000000 _" P P~ @opp-1800000000 kI ~~~ @opp-table-cluster1operating-points-v2 opp-1200000000 G L LB@ @opp-1416000000 Tfr  B@ @opp-1608000000 _" B@ @opp-1800000000 kI P PB@ @opp-2016000000 x) HHB@ @opp-2208000000 h llB@ @opp-2400000000  B@B@B@ @opp-table-cluster2operating-points-v2 opp-1200000000 G L LB@ @opp-1416000000 Tfr  B@ @opp-1608000000 _" B@ @opp-1800000000 kI P PB@ @opp-2016000000 x) HHB@ @opp-2208000000 h llB@ @opp-2400000000  B@B@B@ @opp-tableoperating-points-v2!opp-300000000  L L Popp-400000000 ׄ L L Popp-500000000 e L L Popp-600000000 #F L L Popp-700000000 )' ` ` Popp-800000000 / q q Popp-900000000 5 5 5 Popp-1000000000 ; P P Pchosen !serial2:1500000n8adc-keys adc-keys - 9buttons Jw@ ddbutton-vol-up rVolume Up xs Bhbutton-vol-down rVolume Down xr \button-menu rMenu x button-escape rEscape x 8backlightpwm-backlight  apcie20-avdd0v85-regulatorregulator-fixedpcie20_avdd0v85 P Ppcie20-avdd1v8-regulatorregulator-fixedpcie20_avdd1v8w@w@pcie30-avdd0v75-regulatorregulator-fixedpcie30_avdd0v75 q qpcie30-avdd1v8-regulatorregulator-fixedpcie30_avdd1v8w@w@vcc12v-dcin-regulatorregulator-fixed vcc12v_dcinvcc5v0-host-regulatorregulator-fixed  kdefaulta vcc5v0_hostLK@LK@)vcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@,vcc5v0-usbdcin-regulatorregulator-fixedvcc5v0_usbdcinLK@LK@ vcc5v0-usb-regulatorregulator-fixed vcc5v0_usbLK@LK@ vcc-1v1-nldo-s3-regulatorregulator-fixedvcc_1v1_nldo_s3, compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namespower-domainsstatusdr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosiommusreg-namesrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthmmc-hs400-1_8vmmc-hs400-enhanced-strobeno-sdiono-sdnon-removablerockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellswakeup-sourcenum-csgpio-controller#gpio-cellsspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplypinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplybitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsclock_in_outphy-handlephy-moderx_delaytx_delayreset-assert-usreset-deassert-usreset-gpiosrockchip,phy-grfopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltpower-supplypwmsenable-active-highgpio