G8;L( s;turing,rk1rockchip,rk3588 +7Turing Machines RK1aliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/ethernet@fe1c0000/mmc@fe2e0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0cpuarm,cortex-a55psci"5 < L0,a q~@@  "cpu@100cpuarm,cortex-a55psci"5 a q~@@ "cpu@200cpuarm,cortex-a55psci"5 a q~@@ "cpu@300cpuarm,cortex-a55psci"5 a q~@@ "cpu@400cpuarm,cortex-a76psci"5 < L0,a q~@@"cpu@500cpuarm,cortex-a76psci"5 a q~@@"cpu@600cpuarm,cortex-a76psci"5 < L0,a q~@@"cpu@700cpuarm,cortex-a76psci"5 a q~@@" idle-states*pscicpu-sleeparm,idle-state7H_dpx" l2-cache-l0caches@" l2-cache-l1caches@"l2-cache-l2caches@"l2-cache-l3caches@"l2-cache-b0caches@"l2-cache-b1caches@"l2-cache-b2caches@"l2-cache-b3caches@"l3-cachecaches0@"display-subsystemrockchip,display-subsystemfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smc+protocol@14" protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫splltimerarm,armv8-timerP    % sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram+sram@0arm,scmi-shmem"gpu@fb000000*rockchip,rk3588-maliarm,mali-valhall-csf < L 5!corecoregroupstacks 0\]^  jobmmugpu-  ;disabled!"usb@fc000000rockchip,rk3588-dwc3snps,dwc3@5!ref_clksuspend_clkbus_clkBotg J"#Ousb2-phyusb3-phy Yutmi_wide- bRi ;disabledusb@fc800000"rockchip,rk3588-ehcigeneric-ehci5$J%Ousb-  ;disabledusb@fc840000"rockchip,rk3588-ohcigeneric-ohci5$J%Ousb-  ;disabledusb@fc880000"rockchip,rk3588-ehcigeneric-ehci5&J'Ousb-  ;disabledusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci5&J'Ousb-  ;disabledusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(5jihkr&!ref_clksuspend_clkbus_clkutmipipeBhostJ( Ousb3-phy Yutmi_wideb4i ;disablediommu@fc900000 arm,smmu-v3 @qsvo eventqgerrorpriqcmdq-sync/ ;disablediommu@fcb00000 arm,smmu-v3 @}{ eventqgerrorpriqcmdq-sync/ ;disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdX"lsyscon@fd58c000rockchip,rk3588-sys-grfsysconX"gsyscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ "hsyscon@fd5a6000rockchip,rk3588-vo0-grfsysconZ` 5"syscon@fd5a8000rockchip,rk3588-vo1-grfsysconZ@5"isyscon@fd5ac000rockchip,rk3588-usb-grfsysconZ@"syscon@fd5b0000rockchip,rk3588-php-grfsyscon[")syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon["syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@"syscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsyscon\@"syscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+"usb2phy@0rockchip,rk3588-usb2phy5!phyclk usb480m_phy0bm?+dpower-domain@17 5 x@ABdpower-domain@215 xCDEFGHIJ+dpower-domain@235CAxKdpower-domain@14 5x;dpower-domain@155x<dpower-domain@225xLdpower-domain@245[Z]xMN+dpower-domain@2585ZxOdpower-domain@2685QxPQdpower-domain@2705xRSTU+dpower-domain@28 5xVWdpower-domain@29(5xXYdpower-domain@305z{xZdpower-domain@31@5Wx[\]^dpower-domain@33!5WZ[dpower-domain@34"5WZ[dpower-domain@37%52x_dpower-domain@38&545dpower-domain@40(x`dvideo-codec@fdb50000+rockchip,rk3588-vpu121rockchip,rk3568-vpuw vdpu5 !aclkhclka- iommu@fdb50800,rockchip,rk3588-iommurockchip,rk3568-iommu@v !aclkiface5- /"arga@fdb80000(rockchip,rk3588-rgarockchip,rk3288-rgat5!aclkhclksclkbrqp qos@fdf60400rockchip,rk3588-qossyscon "?qos@fdf61000rockchip,rk3588-qossyscon "@qos@fdf61200rockchip,rk3588-qossyscon "Aqos@fdf61400rockchip,rk3588-qossyscon "Bqos@fdf62000rockchip,rk3588-qossyscon ";qos@fdf63000rockchip,rk3588-qossyscon0 "<qos@fdf64000rockchip,rk3588-qossyscon@ "Kqos@fdf66000rockchip,rk3588-qossyscon` "Cqos@fdf66200rockchip,rk3588-qossysconb "Dqos@fdf66400rockchip,rk3588-qossyscond "Eqos@fdf66600rockchip,rk3588-qossysconf "Fqos@fdf66800rockchip,rk3588-qossysconh "Gqos@fdf66a00rockchip,rk3588-qossysconj "Hqos@fdf66c00rockchip,rk3588-qossysconl "Iqos@fdf66e00rockchip,rk3588-qossysconn "Jqos@fdf67000rockchip,rk3588-qossysconp "Lqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon "5qos@fdf71000rockchip,rk3588-qossyscon "6qos@fdf72000rockchip,rk3588-qossyscon "2qos@fdf72200rockchip,rk3588-qossyscon" "3qos@fdf72400rockchip,rk3588-qossyscon$ "4qos@fdf80000rockchip,rk3588-qossyscon "Oqos@fdf81000rockchip,rk3588-qossyscon "Pqos@fdf81200rockchip,rk3588-qossyscon "Qqos@fdf82000rockchip,rk3588-qossyscon "Mqos@fdf82200rockchip,rk3588-qossyscon" "Ndfi@fe060000rockchip,rk3588-dfi@&0:lpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?05CH>MR)!aclk_mstaclk_slvaclk_dbipclkauxpipepciP syspmcmsglegacyerr`mmmm#4C0n0KJ( Opcie-phy- "T @ @0 @@dbiapbconfigb). `jdefault+;okayregulator@42rockchip,rk8602Bx vdd_npu_s0dp~+regulator-state-memi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c5| !i2cpclk?`jdefault+ ;disabledi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c5} !i2cpclk@`jdefault+ ;disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c5~ !i2cpclkA`jdefault+ ;disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c5 !i2cpclkB`jdefault+ ;disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !5TW !pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt5dc !tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF5!spiclkapb_pclk3,,8txrx `jdefault+ ;disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG5!spiclkapb_pclk3,,8txrx `jdefault+ ;disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH5!spiclkapb_pclk38txrx`jdefault+;okaypmic@0rockchip,rk806B@ jdefault`+++++ + + !+ -+ 9+ F S+ ` m z+  dvs1-null-pins gpio_pwrctrl1 pin_fun0"dvs2-null-pins gpio_pwrctrl2 pin_fun0"dvs3-null-pins gpio_pwrctrl3 pin_fun0"regulatorsdcdc-reg1dp~0 vdd_gpu_s0 regulator-state-memdcdc-reg2dp~0vdd_cpu_lit_s0"regulator-state-memdcdc-reg3 L q0 vdd_log_s0regulator-state-mem qdcdc-reg4dp~0 vdd_vdenc_s0regulator-state-memdcdc-reg5 L 0 vdd_ddr_s0regulator-state-mem Pdcdc-reg6 vdd2_ddr_s3regulator-state-mem dcdc-reg70vdd_2v0_pldo_s3"regulator-state-mem  dcdc-reg82Z2Z vcc_3v3_s3regulator-state-mem  2Zdcdc-reg9 vddq_ddr_s0regulator-state-memdcdc-reg10w@w@ vcc_1v8_s3regulator-state-mem  w@pldo-reg1w@w@ avcc_1v8_s0regulator-state-mempldo-reg2w@w@ vcc_1v8_s0regulator-state-mem w@pldo-reg3OO avdd_1v2_s0regulator-state-mempldo-reg42Z2Z0 vcc_3v3_s0regulator-state-mempldo-reg5w@2Z0 vccio_sd_s0regulator-state-mempldo-reg6w@w@ pldo6_s3regulator-state-mem  w@nldo-reg1 q q vdd_0v75_s3regulator-state-mem  qnldo-reg2 P Pvdd_ddr_pll_s0regulator-state-mem Pnldo-reg3 q q avdd_0v75_s0regulator-state-memnldo-reg4 P P vdd_0v85_s0regulator-state-memnldo-reg5 q q vdd_0v75_s0regulator-state-memspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI5!spiclkapb_pclk38txrx `jdefault+ ;disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL5!baudclkapb_pclk3,, 8txrx`jdefaultLB ;disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM5!baudclkapb_pclk3, , 8txrx`jdefaultLB;okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN5!baudclkapb_pclk3, , 8txrx`jdefaultLB ;disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO5!baudclkapb_pclk3 8txrx`jdefaultLB ;disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP5!baudclkapb_pclk3 8txrx`jdefaultLB ;disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ5!baudclkapb_pclk3 8txrx`jdefaultLB ;disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR5!baudclkapb_pclk3kk8txrx`jdefaultLB ;disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS5!baudclkapb_pclk3k k 8txrx`jdefaultLB ;disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT5!baudclkapb_pclk3k k 8txrx`jdefaultLB;okaypwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5LK !pwmpclk`jdefaultY ;disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5LK !pwmpclk`jdefaultY ;disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5LK !pwmpclk`jdefaultY ;disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05LK !pwmpclk`jdefaultY ;disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5ON !pwmpclk`jdefaultY ;disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5ON !pwmpclk`jdefaultY ;disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5ON !pwmpclk`jdefaultY ;disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05ON !pwmpclk`jdefaultY ;disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5RQ !pwmpclk`jdefaultY ;disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5RQ !pwmpclk`jdefaultY ;disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5RQ !pwmpclk`jdefaultY ;disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05RQ !pwmpclk`jdefaultY ;disabledthermal-zonespackage-thermal   $tripspackage-crit 48 @  criticalbigcore0-thermal d  $tripsbigcore0-alert 4L @ passive"bigcore0-crit 48 @  criticalcooling-mapsmap0 K Pbigcore2-thermal d  $tripsbigcore2-alert 4L @ passive"bigcore2-crit 48 @  criticalcooling-mapsmap0 K P littlecore-thermal d  $tripslittlecore-alert 4L @ passive"littlecore-crit 48 @  criticalcooling-mapsmap0 K0 Pcenter-thermal   $tripscenter-crit 48 @  criticalgpu-thermal d  $tripsgpu-alert 4L @ passive"gpu-crit 48 @  criticalcooling-mapsmap0 K Pnpu-thermal   $tripsnpu-crit 48 @  criticaltsadc@fec00000rockchip,rk3588-tsadc5!tsadcapb_pclk<LbVWEPvcc3v3-pcie30-regulatorregulator-fixedvcc3v3_pcie302Z2Z C [jdefault` V"vcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@"+vcc-1v1-nldo-s3-regulatorregulator-fixedvcc_1v1_nldo_s3+"chosen gserial9:115200n8 compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4ethernet0mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namespower-domainsstatusdr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosiommusreg-namesrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreset-gpiosinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-moderx_delaytx_delayreset-assert-usreset-deassert-ussnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthno-sdiono-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellswakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsvpcie3v3-supplyrockchip,phy-grfopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendcooling-levelsfan-supplypwmsenable-active-highstartup-delay-usstdout-path