-8 ( (friendlyarm,nanopi-r6crockchip,rk3588s +7FriendlyElec NanoPi R6Caliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/ethernet@fe1c0000/mmc@fe2c0000/mmc@fe2e0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0 cpuarm,cortex-a55psci': A Q0,f v@@  'cpu@100 cpuarm,cortex-a55psci': f v@@ 'cpu@200 cpuarm,cortex-a55psci': f v@@ 'cpu@300 cpuarm,cortex-a55psci': f v@@ 'cpu@400 cpuarm,cortex-a76psci': A Q0,f v@@'cpu@500 cpuarm,cortex-a76psci': f v@@'cpu@600 cpuarm,cortex-a76psci': A Q0,f v@@'cpu@700 cpuarm,cortex-a76psci': f v@@' idle-states/pscicpu-sleeparm,idle-state<Mddux' l2-cache-l0cachex@' l2-cache-l1cachex@'l2-cache-l2cachex@'l2-cache-l3cachex@'l2-cache-b0cachex@'l2-cache-b1cachex@'l2-cache-b2cachex@'l2-cache-b3cachex@'l3-cachecachex0@'display-subsystemrockchip,display-subsystemfirmwareopteelinaro,optee-tz smcscmi arm,scmi-smc+protocol@14' protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0 smcclock-0 fixed-clock)׫splltimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram+sram@0arm,scmi-shmem'gpu@fb000000*rockchip,rk3588-maliarm,mali-valhall-csf A Q :&corecoregroupstacks 0\]^ jobmmugpu2  @disabled!'usb@fc000000rockchip,rk3588-dwc3snps,dwc3@:&ref_clksuspend_clkbus_clkGotg O"#Tusb2-phyusb3-phy ^utmi_wide2 gRn @disabledusb@fc800000"rockchip,rk3588-ehcigeneric-ehci:$O%Tusb2 @okayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci:$O%Tusb2 @okayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci:&O'Tusb2  @disabledusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci:&O'Tusb2  @disabledusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(:jihkr&&ref_clksuspend_clkbus_clkutmipipeGhostO( Tusb3-phy ^utmi_wideg4n @disablediommu@fc900000 arm,smmu-v3 @qsvoeventqgerrorpriqcmdq-sync4 @disablediommu@fcb00000 arm,smmu-v3 @}{eventqgerrorpriqcmdq-sync4 @disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdX'msyscon@fd58c000rockchip,rk3588-sys-grfsysconX'hsyscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ 'isyscon@fd5a6000rockchip,rk3588-vo0-grfsysconZ` :'syscon@fd5a8000rockchip,rk3588-vo1-grfsysconZ@:'jsyscon@fd5ac000rockchip,rk3588-usb-grfsysconZ@'syscon@fd5b0000rockchip,rk3588-php-grfsyscon['*syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon['syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@'syscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsyscon\@'syscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+'usb2phy@0rockchip,rk3588-usb2phy:&phyclk usb480m_phy0gmAphyapb @disabled'otg-portM @disabled'"syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@8000rockchip,rk3588-usb2phy:&phyclk usb480m_phy2goAphyapb@okay'$host-portM@okayX)'%syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@c000rockchip,rk3588-usb2phy:&phyclk usb480m_phy3gp Aphyapb @disabled'&host-portM @disabled''syscon@fd5e0000$rockchip,rk3588-hdptxphy-grfsyscon^'syscon@fd5f0000rockchip,rk3588-iocsyscon_'sram@fd600000 mmio-sram``+clock-controller@fd7c0000rockchip,rk3588-cru|A]q@QA.2Fq)׫ׄe/ׄ eZ р c*'i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=:ts &i2cpclkp+zdefault+@okayregulator@42rockchip,rk8602Bvdd_cpu_big0_s0dp ,'regulator-state-mem*regulator@43 rockchip,rk8603rockchip,rk8602Cvdd_cpu_big1_s0dp ,'regulator-state-mem*serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK:&baudclkapb_pclkC--Htxrxp.zdefaultR\ @disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm: &pwmpclkp/zdefaulti @disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm: &pwmpclkp0zdefaulti @disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm : &pwmpclkp1zdefaulti @disabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0: &pwmpclkp2zdefaulti @disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfd'kpower-controller!rockchip,rk3588-power-controllert+@okay' power-domain@8t+power-domain@9  :!#" 345t+power-domain@10 :!#"6tpower-domain@11 :!#"7tpower-domain@12 :89:;tpower-domain@13 +tpower-domain@14(:<tpower-domain@15 :=tpower-domain@16: >?@+tpower-domain@17 : ABCtpower-domain@21: DEFGHIJK+tpower-domain@23:CALtpower-domain@14 :<tpower-domain@15:=tpower-domain@22:Mtpower-domain@24:[Z]NO+tpower-domain@258:ZPtpower-domain@268:QQRtpower-domain@270:STUV+tpower-domain@28 :WXtpower-domain@29(:YZtpower-domain@30:z{[tpower-domain@31@:W\]^_tpower-domain@33!:WZ[tpower-domain@34":WZ[tpower-domain@37%:2`tpower-domain@38&:45tpower-domain@40(atvideo-codec@fdb50000+rockchip,rk3588-vpu121rockchip,rk3568-vpuwvdpu: &aclkhclkb2 iommu@fdb50800,rockchip,rk3588-iommurockchip,rk3568-iommu@v &aclkiface:2 4'brga@fdb80000(rockchip,rk3588-rgarockchip,rk3288-rgat:&aclkhclksclkgrqp Acoreaxiahb2 video-codec@fdba0000rockchip,rk3588-vepu121z: &aclkhclkc2 iommu@fdba0800,rockchip,rk3588-iommurockchip,rk3568-iommu@y: &aclkiface2 4'cvideo-codec@fdba4000rockchip,rk3588-vepu121@|: &aclkhclkd2 iommu@fdba4800,rockchip,rk3588-iommurockchip,rk3568-iommuH@{: &aclkiface2 4'dvideo-codec@fdba8000rockchip,rk3588-vepu121~: &aclkhclke2 iommu@fdba8800,rockchip,rk3588-iommurockchip,rk3568-iommu@}: &aclkiface2 4'evideo-codec@fdbac000rockchip,rk3588-vepu121: &aclkhclkf2 iommu@fdbac800,rockchip,rk3588-iommurockchip,rk3568-iommu@: &aclkiface2 4'fvideo-codec@fdc70000rockchip,rk3588-av1-vpulvdpuAACQׄׄ:AC &aclkhclk2  gvop@fdd90000rockchip,rk3588-vop BPvopgamma-lut8:]\abcd[7&aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vopg2 chijk @disabledports+'port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~:]\ &aclkiface42  @disabled'gi2s@fddc0000rockchip,rk3588-i2s-tdm:&mclk_txmclk_rxhclkAClHtx2 gAtx-m @disabledi2s@fddf0000rockchip,rk3588-i2s-tdm:445&mclk_txmclk_rxhclkA1ClHtx2 gAtx-m @disabledi2s@fddfc000rockchip,rk3588-i2s-tdm:00,&mclk_txmclk_rxhclkA-ClHrx2 gArx-m @disabledqos@fdf35000rockchip,rk3588-qossysconP '8qos@fdf35200rockchip,rk3588-qossysconR '9qos@fdf35400rockchip,rk3588-qossysconT ':qos@fdf35600rockchip,rk3588-qossysconV ';qos@fdf36000rockchip,rk3588-qossyscon` '[qos@fdf39000rockchip,rk3588-qossyscon '`qos@fdf3d800rockchip,rk3588-qossyscon 'aqos@fdf3e000rockchip,rk3588-qossyscon ']qos@fdf3e200rockchip,rk3588-qossyscon '\qos@fdf3e400rockchip,rk3588-qossyscon '^qos@fdf3e600rockchip,rk3588-qossyscon '_qos@fdf40000rockchip,rk3588-qossyscon 'Yqos@fdf40200rockchip,rk3588-qossyscon 'Zqos@fdf40400rockchip,rk3588-qossyscon 'Sqos@fdf40500rockchip,rk3588-qossyscon 'Tqos@fdf40600rockchip,rk3588-qossyscon 'Uqos@fdf40800rockchip,rk3588-qossyscon 'Vqos@fdf41000rockchip,rk3588-qossyscon 'Wqos@fdf41100rockchip,rk3588-qossyscon 'Xqos@fdf60000rockchip,rk3588-qossyscon '>qos@fdf60200rockchip,rk3588-qossyscon '?qos@fdf60400rockchip,rk3588-qossyscon '@qos@fdf61000rockchip,rk3588-qossyscon 'Aqos@fdf61200rockchip,rk3588-qossyscon 'Bqos@fdf61400rockchip,rk3588-qossyscon 'Cqos@fdf62000rockchip,rk3588-qossyscon '<qos@fdf63000rockchip,rk3588-qossyscon0 '=qos@fdf64000rockchip,rk3588-qossyscon@ 'Lqos@fdf66000rockchip,rk3588-qossyscon` 'Dqos@fdf66200rockchip,rk3588-qossysconb 'Eqos@fdf66400rockchip,rk3588-qossyscond 'Fqos@fdf66600rockchip,rk3588-qossysconf 'Gqos@fdf66800rockchip,rk3588-qossysconh 'Hqos@fdf66a00rockchip,rk3588-qossysconj 'Iqos@fdf66c00rockchip,rk3588-qossysconl 'Jqos@fdf66e00rockchip,rk3588-qossysconn 'Kqos@fdf67000rockchip,rk3588-qossysconp 'Mqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon '6qos@fdf71000rockchip,rk3588-qossyscon '7qos@fdf72000rockchip,rk3588-qossyscon '3qos@fdf72200rockchip,rk3588-qossyscon" '4qos@fdf72400rockchip,rk3588-qossyscon$ '5qos@fdf80000rockchip,rk3588-qossyscon 'Pqos@fdf81000rockchip,rk3588-qossyscon 'Qqos@fdf81200rockchip,rk3588-qossyscon 'Rqos@fdf82000rockchip,rk3588-qossyscon 'Nqos@fdf82200rockchip,rk3588-qossyscon" 'Odfi@fe060000rockchip,rk3588-dfi@&0:mpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0:CH>MR)&aclk_mstaclk_slvaclk_dbipclkauxpipe pciPsyspmcmsglegacyerr`%nnnn3DS0o0[O( Tpcie-phy2 "T @ @0 @@dbiapbconfigg). Apwrpipe+@okay epqqlegacy-interrupt-controller 'npcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O0:DI?NSs)&aclk_mstaclk_slvaclk_dbipclkauxpipe pciPsyspmcmsglegacyerr`%rrrr3DS@o@[Os Tpcie-phy2 "T @ @0 A@dbiapbconfigg*/ Apwrpipe+@okay etqqlegacy-interrupt-controller 'rethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(:67Y^50&stmmacethclk_mac_refpclk_macaclk_macptp_ref2 !g$ Astmmacethch*uvw@okayoutputx rgmii-rxidpyz{|}zdefaultBmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916zdefaultp~!N 1 et'xstmmac-axi-configCM]'urx-queues-configm'vqueue0queue1tx-queues-config'wqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci!(:b_eTo&satapmaliverxoobrefasic+ @disabledsata-port@0@Os Tsata-phy  sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(:dagVq&satapmaliverxoobrefasic+ @disabledsata-port@0@O( Tsata-phy  spi@fe2b0000 rockchip,sfc+@:/0&clk_sfchclk_sfc+ @disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ :  &biuciuciu-driveciu-sampleрzdefaultp2 (@okay $2>mmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ :&biuciuciu-driveciu-sample zdefaultp2 % @disabledmmc@fe2e0000rockchip,rk3588-dwcmshc.A-., Q n6 (:,*+-.&corebusaxiblocktimer pzdefault(gAcorebusaxiblocktimer@okayKQ_i2s@fe470000rockchip,rk3588-i2s-tdmG:+/(&mclk_txmclk_rxhclkA)-C--Htxrx2 &g*+ Atx-mrx-mnzdefault(p @disabledi2s@fe480000rockchip,rk3588-i2s-tdmH:y}u&mclk_txmclk_rxhclkC--Htxrxg^_ Atx-mrx-mnzdefault(p @disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI:&i2s_clki2s_hclkACHtxrx2 &zdefaultp @disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ:%&i2s_clki2s_hclkA"CHtxrx2 &zdefaultp @disabledinterrupt-controller@fe600000 arm,gic-v3 `h a8+'msi-controller@fe640000arm,gic-v3-itsd'omsi-controller@fe660000arm,gic-v3-itsfppi-partitionsinterrupt-partition-0'interrupt-partition-1 'dma-controller@fea10000arm,pl330arm,primecell@ VW:n &apb_pclk'-dma-controller@fea30000arm,pl330arm,primecell@ XY:o &apb_pclk'i2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c:{ &i2cpclk>pzdefault+ @disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c:| &i2cpclk?pzdefault+@okayregulator@42rockchip,rk8602B vdd_npu_s0dp~ ,regulator-state-mem*i2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c:} &i2cpclk@pzdefault+ @disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c:~ &i2cpclkApzdefault+ @disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c: &i2cpclkBpzdefault+ @disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !:TW &pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt:dc &tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF:&spiclkapb_pclkC--Htxrx pzdefault+ @disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG:&spiclkapb_pclkC--Htxrx pzdefault+ @disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH:&spiclkapb_pclkCHtxrxpzdefault+@okayAQ pmic@0rockchip,rk806B@ zdefaultp , , ,, 8, D, P, \, h, t, ,  ,   ,  dvs1-null-pins gpio_pwrctrl1 pin_fun0'dvs2-null-pins gpio_pwrctrl2 pin_fun0'dvs3-null-pins gpio_pwrctrl3 pin_fun0'regulatorsdcdc-reg1dp~ 0 vdd_gpu_s0 regulator-state-mem*dcdc-reg2dp~ 0vdd_cpu_lit_s0'regulator-state-mem*dcdc-reg3 L q 0 vdd_log_s0regulator-state-mem*  qdcdc-reg4dp~ 0 vdd_vdenc_s0regulator-state-mem*dcdc-reg5 L  0 vdd_ddr_s0regulator-state-mem*  Pdcdc-reg6 vdd2_ddr_s3regulator-state-mem /dcdc-reg7 0vdd_2v0_pldo_s3'regulator-state-mem / dcdc-reg82Z2Z vcc_3v3_s3'regulator-state-mem / 2Zdcdc-reg9 vddq_ddr_s0regulator-state-mem*dcdc-reg10w@w@ vcc_1v8_s3regulator-state-mem / w@pldo-reg1w@w@ avcc_1v8_s0'regulator-state-mem* w@pldo-reg2w@w@ vcc_1v8_s0regulator-state-mem* w@pldo-reg3OO avdd_1v2_s0regulator-state-mem*pldo-reg42Z2Z 0 avcc_3v3_s0regulator-state-mem*pldo-reg5w@2Z 0 vccio_sd_s0'regulator-state-mem*pldo-reg6w@w@ pldo6_s3regulator-state-mem / w@nldo-reg1 q q vdd_0v75_s3regulator-state-mem /  qnldo-reg2 P Pavdd_ddr_pll_s0regulator-state-mem*  Pnldo-reg3 q q avdd_0v75_s0regulator-state-mem*nldo-reg4 P P avdd_0v85_s0regulator-state-mem*nldo-reg5 q q vdd_0v75_s0regulator-state-mem*spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI:&spiclkapb_pclkCHtxrx pzdefault+ @disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL:&baudclkapb_pclkC-- Htxrxpzdefault\R @disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM:&baudclkapb_pclkC- - Htxrxpzdefault\R@okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN:&baudclkapb_pclkC- - Htxrxpzdefault\R @disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO:&baudclkapb_pclkC Htxrxpzdefault\R @disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP:&baudclkapb_pclkC Htxrxpzdefault\R @disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ:&baudclkapb_pclkC Htxrxpzdefault\R @disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR:&baudclkapb_pclkCllHtxrxpzdefault\R @disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS:&baudclkapb_pclkCl l Htxrxpzdefault\R @disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT:&baudclkapb_pclkCl l Htxrxpzdefault\R @disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm:LK &pwmpclkpzdefaulti @disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm:LK &pwmpclkpzdefaulti @disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm :LK &pwmpclkpzdefaulti @disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0:LK &pwmpclkpzdefaulti @disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm:ON &pwmpclkpzdefaulti @disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm:ON &pwmpclkpzdefaulti @disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm :ON &pwmpclkpzdefaulti @disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0:ON &pwmpclkpzdefaulti @disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm:RQ &pwmpclkpzdefaulti @disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm:RQ &pwmpclkpzdefaulti @disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm :RQ &pwmpclkpzdefaulti @disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0:RQ &pwmpclkpzdefaulti @disabledthermal-zonespackage-thermal G ] ktripspackage-crit {8  criticalbigcore0-thermal Gd ] ktripsbigcore0-alert {L passive'bigcore0-crit {8  criticalcooling-mapsmap0  bigcore2-thermal Gd ] ktripsbigcore2-alert {L passive'bigcore2-crit {8  criticalcooling-mapsmap0   littlecore-thermal Gd ] ktripslittlecore-alert {L passive'littlecore-crit {8  criticalcooling-mapsmap0 0 center-thermal G ] ktripscenter-crit {8  criticalgpu-thermal Gd ] ktripsgpu-alert {L passive'gpu-crit {8  criticalcooling-mapsmap0  npu-thermal G ] ktripsnpu-crit {8  criticaltsadc@fec00000rockchip,rk3588-tsadc:&tsadcapb_pclkAQgVWAtsadc-apbtsadc   p  zgpiootpout @okay'adc@fec10000rockchip,rk3588-saradc :&saradcapb_pclkgU Asaradc-apb@okay !'i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c: &i2cpclkCpzdefault+@okay @rtc@51haoyu,hym8563Qhym8563zdefaultp  -i2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c: &i2cpclkDpzdefault+ @disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c: &i2cpclkEpzdefault+ @disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ:&spiclkapb_pclkCl lHtxrx pzdefault+ @disabledefuse@fecc0000rockchip,rk3588-otp :&otpapb_pclkphyarbg Aotpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c ;npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[:p &apb_pclk'lphy@fed60000rockchip,rk3588-hdptx-phy :T&refapbM8g#cde!""Aphyapbinitcmnlaneroplllcpllc @disabledphy@fed80000rockchip,rk3588-usbdp-phyM:lV&refclkimmortalpclkutmi(g   Ainitcmnlanepcs_apbpma_apb @ S d z @disabled'#phy@fee00000rockchip,rk3588-naneng-combphy:vW &refapbpipeAQMg<CAphyapb * @okay'sphy@fee20000rockchip,rk3588-naneng-combphy:xW &refapbpipeAQMg>EAphyapb * @okay'(sram@ff001000 mmio-sram+pinctrlrockchip,rk3588-pinctrlc+'gpio@fd8a0000rockchip,gpio-bank:qr   'gpio@fec20000rockchip,gpio-bank:st   'pgpio@fec30000rockchip,gpio-bank:uv  @  gpio@fec40000rockchip,gpio-bank:wx  `  'tgpio@fec50000rockchip,gpio-bank:yz   'pcfg-pull-up 'pcfg-pull-down 'pcfg-pull-none 'pcfg-pull-none-drv-level-2  'pcfg-pull-up-drv-level-1  'pcfg-pull-up-drv-level-2  'pcfg-pull-none-smt  'auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout 'emmc-bus8 'emmc-clk 'emmc-cmd 'emmc-data-strobe 'eth1fspigmac1gmac1-miim 'ygmac1-rx-bus20  '{gmac1-tx-bus20    'zgmac1-rgmii-clk '|gmac1-rgmii-bus@ '}gpuhdmii2c0i2c0m2-xfer '+i2c1i2c1m0-xfer  'i2c2i2c2m0-xfer   'i2c3i2c3m0-xfer   'i2c4i2c4m0-xfer   'i2c5i2c5m0-xfer   'i2c6i2c6m0-xfer   'i2c7i2c7m0-xfer   'i2c8i2c8m0-xfer   'i2s0i2s0-lrck 'i2s0-sclk 'i2s0-sdi0 'i2s0-sdi1 'i2s0-sdi2 'i2s0-sdi3 'i2s0-sdo0 'i2s0-sdo1 'i2s0-sdo2 'i2s0-sdo3 'i2s1i2s1m0-lrck 'i2s1m0-sclk 'i2s1m0-sdi0 'i2s1m0-sdi1 'i2s1m0-sdi2 'i2s1m0-sdi3 'i2s1m0-sdo0  'i2s1m0-sdo1  'i2s1m0-sdo2  'i2s1m0-sdo3  'i2s2i2s2m1-lrck 'i2s2m1-sclk  'i2s2m1-sdi  'i2s2m1-sdo  'i2s3i2s3-lrck 'i2s3-sclk 'i2s3-sdi 'i2s3-sdo 'jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp 'pmupwm0pwm0m0-pins '/pwm1pwm1m0-pins '0pwm2pwm2m0-pins '1pwm3pwm3m0-pins '2pwm4pwm4m0-pins  'pwm5pwm5m0-pins 'pwm6pwm6m0-pins  'pwm7pwm7m0-pins  'pwm8pwm8m0-pins  'pwm9pwm9m0-pins  'pwm10pwm10m0-pins  'pwm11pwm11m0-pins  'pwm12pwm12m0-pins  'pwm13pwm13m0-pins  'pwm14pwm14m0-pins  'pwm15pwm15m0-pins  'refclksatasata0sata1sata2sdiosdiom1-pins` 'sdmmcsdmmc-bus4@ 'sdmmc-clk 'sdmmc-cmd 'sdmmc-det 'sd-s0-pwr  'spdif0spdif1spi0spi0m0-pins0 'spi0m0-cs0 'spi0m0-cs1 'spi1spi1m1-pins0 'spi1m1-cs0 'spi1m1-cs1 'spi2spi2m2-pins0  'spi2m2-cs0 'spi3spi3m1-pins0  'spi3m1-cs0 'spi3m1-cs1 'spi4spi4m0-pins0 'spi4m0-cs0 'spi4m0-cs1 'tsadctsadc-shut 'uart0uart0m1-xfer  '.uart1uart1m1-xfer   'uart2uart2m0-xfer  'uart3uart3m1-xfer   'uart4uart4m1-xfer   'uart5uart5m1-xfer   'uart6uart6m1-xfer   'uart7uart7m1-xfer   'uart8uart8m1-xfer   'uart9uart9m1-xfer   'vopbt656gpio-functsadc-gpio-func 'gpio-keykey1-pin 'gpio-ledssys-led-pin 'wan-led-pin 'lan1-led-pin 'lan2-led-pin 'hym8563rtc-int 'usbtypec5v-pwren 'vcc5v0-host20-en  'rtl8211frtl8211f-rst '~opp-table-cluster0operating-points-v2 ' opp-1008000000 $< + L L~ 9@opp-1200000000 $G + 4 4~ 9@opp-1416000000 $Tfr + ~ 9@ Jopp-1608000000 $_" + P P~ 9@opp-1800000000 $kI +~~~ 9@opp-table-cluster1operating-points-v2 'opp-1200000000 $G + L LB@ 9@opp-1416000000 $Tfr +  B@ 9@opp-1608000000 $_" + B@ 9@opp-1800000000 $kI + P PB@ 9@opp-2016000000 $x) +HHB@ 9@opp-2208000000 $h +llB@ 9@opp-2400000000 $  +B@B@B@ 9@opp-table-cluster2operating-points-v2 'opp-1200000000 $G + L LB@ 9@opp-1416000000 $Tfr +  B@ 9@opp-1608000000 $_" + B@ 9@opp-1800000000 $kI + P PB@ 9@opp-2016000000 $x) +HHB@ 9@opp-2208000000 $h +llB@ 9@opp-2400000000 $  +B@B@B@ 9@opp-tableoperating-points-v2'!opp-300000000 $ + L L Popp-400000000 $ׄ + L L Popp-500000000 $e + L L Popp-600000000 $#F + L L Popp-700000000 $)' + ` ` Popp-800000000 $/ + q q Popp-900000000 $5 + 5 5 Popp-1000000000 $; + P P Pchosen Vserial2:1500000n8adc-keys adc-keys b nbuttons w@ dbutton-maskrom Maskrom h gpio-keys gpio-keyszdefaultpbutton-user User  kp 2leds gpio-ledsled-0 sys_led kp heartbeatzdefaultpled-1 wan_led kpzdefaultpled-2 lan1_led kpzdefaultpled-3 user_led kpzdefaultpvcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@',vcc-1v1-nldo-s3-regulatorregulator-fixedvcc_1v1_nldo_s3,'vcc-3v3-s0-regulatorregulator-fixed2Z2Z vcc_3v3_s0vcc-3v3-sd-s0-regulatorregulator-fixed  k zdefaultpvcc_3v3_sd_s0--'vcc3v3-pcie20-regulatorregulator-fixedvcc_3v3_pcie202Z2Z'qvcc5v0-usb-regulatorregulator-fixed vcc5v0_usbLK@LK@,'vcc5v0-usb-otg0-regulatorregulator-fixed  kpzdefaultpvcc5v0_usb_otg0LK@LK@vcc5v0-host-20-regulatorregulator-fixed  k zdefaultpvcc5v0_host_20LK@LK@') compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4ethernet0mmc0mmc1cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namespower-domainsstatusdr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosiommusreg-namesrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplyinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modetx_delayreset-assert-usreset-deassert-ussnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpno-mmcno-sdiosd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs200-1_8vrockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplywakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltdebounce-intervallinux,default-triggerenable-active-high