:884(7 ,Unisoc UMS512-1H10 Board2sprd,ums512-1h10sprd,ums512cpus cpu-mapcluster0core0=core1=core2=core3=core4=core5=core6=core7= cpu@0Acpu2arm,cortex-a55MQpsci_ ocpu@100Acpu2arm,cortex-a55MQpsci_ ocpu@200Acpu2arm,cortex-a55MQpsci_ ocpu@300Acpu2arm,cortex-a55MQpsci_ ocpu@400Acpu2arm,cortex-a55MQpsci_ ocpu@500Acpu2arm,cortex-a55MQpsci_ ocpu@600Acpu2arm,cortex-a75MQpsci_ ocpu@700Acpu2arm,cortex-a75MQpsci_ o idle-stateswpscicpu-pd2arm,idle-state'o psci 2arm,psci-0.2Xsmctimer2arm,armv8-timer0   pmu-a552arm,cortex-a55-pmuHpqrstupmu-a752arm,cortex-a75-pmuvw soc 2simple-bus interrupt-controller@12000000 2arm,gic-v3 M )@  osyscon@20100000&2sprd,ums512-glbregssysconsimple-mfdM @  @clock-controller@02sprd,ums512-apahb-gateM0U \ext-26mhsyscon@31050000&2sprd,ums512-glbregssysconsimple-mfdM1syscon@322a0000&2sprd,ums512-glbregssysconsimple-mfdM2*syscon@32310000&2sprd,ums512-glbregssysconsimple-mfdM21syscon@32320000&2sprd,ums512-glbregssysconsimple-mfdM22syscon@32330000&2sprd,ums512-glbregssysconsimple-mfdM23syscon@32340000&2sprd,ums512-glbregssysconsimple-mfdM24syscon@32350000&2sprd,ums512-glbregssysconsimple-mfdM25syscon@32360000&2sprd,ums512-glbregssysconsimple-mfdM26syscon@32390000&2sprd,ums512-glbregssysconsimple-mfdM290 290clock-controller@02sprd,ums512-g0-pllMhsyscon@323b0000&2sprd,ums512-glbregssysconsimple-mfdM2;0 2;0clock-controller@02sprd,ums512-g2-pllMhsyscon@323c0000&2sprd,ums512-glbregssysconsimple-mfdM2<0 2<0clock-controller@02sprd,ums512-g3-pllM0U \ext-26mho-syscon@323e0000&2sprd,ums512-glbregssysconsimple-mfdM2>0 2>0clock-controller@02sprd,ums512-gc-pllMU \ext-26mhsyscon@323f0000&2sprd,ums512-glbregssysconsimple-mfdM2?0syscon@327d0000&2sprd,ums512-glbregssysconsimple-mfdM2}0 2}0clock-controller@02sprd,ums512-aon-gateM0U \ext-26mhsyscon@327e0000&2sprd,ums512-glbregssysconsimple-mfdM2~0 2~0clock-controller@02sprd,ums512-pmu-gateM0U \ext-26mhsyscon@3350d000&2sprd,ums512-glbregssysconsimple-mfdM3P 3Pclock-controller@02sprd,ums512-audcpapb-gateMhsyscon@335e0000&2sprd,ums512-glbregssysconsimple-mfdM3^ 3^clock-controller@02sprd,ums512-audcpahb-gateMhsyscon@60100000&2sprd,ums512-glbregssysconsimple-mfdM`0 `0clock-controller@02sprd,ums512-gpu-clkU \ext-26mMhsyscon@60110000&2sprd,ums512-glbregssysconsimple-mfdM`0syscon@62200000&2sprd,ums512-glbregssysconsimple-mfdMb 0 b 0clock-controller@02sprd,ums512-mm-gate-clkM0hsyscon@71000000&2sprd,ums512-glbregssysconsimple-mfdMq0 q0clock-controller@02sprd,ums512-apapb-gateM0ho,clock-controller@202000002sprd,ums512-ap-clkM U \ext-26mho+clock-controller@320800002sprd,ums512-aonapb-clkM2U  \ext-26mext-32kext-4mrco-100mhclock-controller@621000002sprd,ums512-mm-clkMbU \ext-26mhfunnel@3c002000+2arm,coresight-dynamic-funnelarm,primecellM< U  \apb_pclkout-portsportendpointuoin-ports port@1Mendpointuoetb@3c003000 2arm,coresight-tmcarm,primecellM<0U  \apb_pclkin-portsportendpointuofunnel@3e001000+2arm,coresight-dynamic-funnelarm,primecellM>U  \apb_pclkout-portsportendpointuoin-ports port@0Mendpointuo&port@1Mendpointuo'port@2Mendpointuo(port@3Mendpointuo*etf@3e002000 2arm,coresight-tmcarm,primecellM> U  \apb_pclkout-portsportendpointuoin-portsportendpointuoetf@3e003000 2arm,coresight-tmcarm,primecellM>0U  \apb_pclkout-portsportendpointuoin-portsportendpointuofunnel@3e004000+2arm,coresight-dynamic-funnelarm,primecellM>@U  \apb_pclkout-portsportendpointuoin-ports port@0Mendpointuoport@1Mendpointuofunnel@3e005000+2arm,coresight-dynamic-funnelarm,primecellM>PU  \apb_pclkout-portsportendpointuoin-ports port@0Mendpointuo#port@1Mendpointu o$port@2Mendpointu!o%port@3Mendpointu"o)etm@3f040000"2arm,coresight-etm4xarm,primecellM?=U  \apb_pclkout-portsportendpointu#oetm@3f140000"2arm,coresight-etm4xarm,primecellM?=U  \apb_pclkout-portsportendpointu$o etm@3f240000"2arm,coresight-etm4xarm,primecellM?$=U  \apb_pclkout-portsportendpointu%o!etm@3f340000"2arm,coresight-etm4xarm,primecellM?4=U  \apb_pclkout-portsportendpointu&oetm@3f440000"2arm,coresight-etm4xarm,primecellM?D=U  \apb_pclkout-portsportendpointu'oetm@3f540000"2arm,coresight-etm4xarm,primecellM?T=U  \apb_pclkout-portsportendpointu(oetm@3f640000"2arm,coresight-etm4xarm,primecellM?d=U  \apb_pclkout-portsportendpointu)o"etm@3f740000"2arm,coresight-etm4xarm,primecellM?t= U  \apb_pclkout-portsportendpointu*oapb@70000000 2simple-bus pserial@0"2sprd,ums512-uartsprd,sc9836-uartM U okayserial@100000"2sprd,ums512-uartsprd,sc9836-uartM U okaymmc@11000002sprd,sdhci-r11M U+, \sdioenable+- disabledsrrn!mmc@14000002sprd,sdhci-r11M@ U+, \sdioenable+-okay7=Kbus@32000000 2simple-bus 2spi@1000002sprd,ums512-adiM P\ TtDDd #'clk-26m 2fixed-clockhm}ext-26mo clk-32k 2fixed-clockhm}ext-32ko clk-4m 2fixed-clockhm= }ext-4mo clk-100m 2fixed-clockhm }rco-100moaliases/soc/apb@70000000/serial@0 /soc/apb@70000000/serial@100000memory@80000000AmemoryMchosenserial1:115200n8 interrupt-parent#address-cells#size-cellsmodelcompatiblecpudevice_typeregenable-methodcpu-idle-statesphandleentry-methodentry-latency-usexit-latency-usmin-residency-uslocal-timer-stoparm,psci-suspend-paraminterruptsinterrupt-affinityranges#interrupt-cellsredistributor-stride#redistributor-regionsinterrupt-controllerclocksclock-names#clock-cellsremote-endpointstatusassigned-clocksassigned-clock-parentsbus-widthno-sdiono-mmcsprd,phy-delay-sd-uhs-sdr104sprd,phy-delay-sd-uhs-sdr50sprd,phy-delay-sd-highspeedsprd,phy-delay-legacyno-sdnon-removablecap-mmc-hw-resetsprd,hw-channelsclock-frequencyclock-output-namesserial0serial1stdout-path