~u8w@(5w  ,Xiaomi Mi A3!2xiaomi,laurel-sproutqcom,sm6125=handsetJV chosen dframebuffer@5c0000002simple-framebufferk\Dou| @ a8r8g8b8clocksxo-board 2fixed-clock$sleep-clk 2fixed-clock} sleep_clkcpus cpu@0cpu 2qcom,kryo260kpscil2-cache2cache cpu@1cpu 2qcom,kryo260kpscicpu@2cpu 2qcom,kryo260kpscicpu@3cpu 2qcom,kryo260kpscicpu@100cpu 2qcom,kryo260kpscifl2-cache2cache cpu@101cpu 2qcom,kryo260kpscif cpu@102cpu 2qcom,kryo260kpscif cpu@103cpu 2qcom,kryo260kpscif cpu-mapcluster0core0core1core2core3cluster1core0core1 core2 core3 firmwarescm2qcom,scm-sm6125qcom,scmmemory@40000000k@memorypmu2arm,armv8-pmuv3 +psci 2arm,psci-1.0smcremoteproc#2qcom,sm6125-rpm-procqcom,rpm-procglink-edge2qcom,glink-rpm +6 G rpm-requests#2qcom,rpm-sm6125qcom,glink-smd-rpm Nrpm_requestsclock-controller2qcom,rpmcc-sm6125qcom,rpmccbixopower-controller2qcom,sm6125-rpmpduopp-table2operating-points-v2opp1Yopp2 opp30opp4@Qopp5Ropp6Sopp7Topp8@opp9Uopp10regulators-02qcom,rpm-pm6125-regulatorss6H@l1O*@l2B@l3B@<@l4 N@(l5%-p"l6 l7 N@l8 l9w@@l10w@@l11w@%l12w@tl13w@@l14w@ l15/]1Ql16w@ l17 l18OI&l19%- @l20%- @l21'@+@l22,-p!l23-3@l24,-p$reserved-memory dmemory@45700000kEp`memory@45e00000kEmemory@45fff000kEmemory@46000000kF memory@46200000kF memory@4ab00000kJPmemory@4b000000kKmemory@52e00000kRPmemory@53300000kS0 memory@53500000kSPmemory@55300000kU0memory@57100000kWmemory@57110000kWPmemory@57115000kWP memory@5c000000k\memory@5cf00000k\memory@5f800000k_memory@5e400000k^@@memory@f3000000k@memory@f3400000k@memory@13fc00000k?@debug@ffb00000k lastlog@ffbc0000kramoops@ffc000002ramoopsk memory@ffd00000ksmem 2qcom,smem(soc@0 d 2simple-bushwlock@3400002qcom,tcsr-mutexk40pinctrl@5000002qcom,sm6125-tlmmkP@@@>westsoutheast +HXdpsdc2-off-state clk-pins sdc2_clkcmd-pins sdc2_cmddata-pins sdc2_datasd-cd-pinsgpio98gpiosdc2-on-stateclk-pins sdc2_clkcmd-pins sdc2_cmd data-pins sdc2_data sd-cd-pinsgpio98gpioqup-i2c0-default-state gpio0gpio1qup00)qup-i2c0-sleep-state gpio0gpio1gpio*qup-i2c1-default-state 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interrupt-parent#address-cells#size-cellsmodelcompatiblechassis-typeqcom,msm-idqcom,board-idrangesregwidthheightstrideformat#clock-cellsclock-frequencyphandleclock-output-namesdevice_typeenable-methodcapacity-dmips-mhznext-level-cachecache-levelcache-unifiedcpu#reset-cellsinterruptsqcom,rpm-msg-rammboxesqcom,glink-channelsclocksclock-names#power-domain-cellsoperating-points-v2opp-levelregulator-min-microvoltregulator-max-microvoltregulator-allow-set-loadno-maprecord-sizeconsole-sizepmsg-sizememory-regionhwlocks#hwlock-cellsreg-namesgpio-controllergpio-ranges#gpio-cellsinterrupt-controller#interrupt-cellsgpio-reserved-rangespinsdrive-strengthbias-disablebias-pull-upfunction#phy-cellsresetsstatusvdd-supplyvdda-pll-supplyvdda-phy-dpdm-supplyinterrupt-namesqcom,eeqcom,channelmode-bootloadermode-recoverydebouncelinux,codeio-channelsio-channel-names#thermal-sensor-cells#io-channel-cellspinctrl-namespinctrl-0qcom,pre-scalinglabelqcom,hw-settle-timeqcom,ratiometricqcom,hw-settle-time-usbias-high-impedanceinput-enableiommuspower-domainsqcom,dll-configqcom,ddr-configbus-widthnon-removablesupports-cqepinctrl-1cd-gpiosvmmc-supplyvqmmc-supplyno-sdiono-mmcfreq-table-hzreset-namesphysphy-nameslanes-per-directionvcc-supplyvccq2-supplyvcc-max-microampvccq2-max-microampvdd-hba-supplyvdda-phy-supplydma-channelsdma-channel-mask#dma-cellsdmasdma-namesassigned-clocksassigned-clock-ratesqcom,select-utmi-as-pipe-clksnps,dis_u2_susphy_quirksnps,dis_enblslpm_quirkmaximum-speeddr_modeextconremote-endpointopp-hzrequired-oppsassigned-clock-parents#global-interrupts#iommu-cells#mbox-cellsframe-numberpolling-delay-passivethermal-sensorstemperaturehysteresisid-gpiosdebounce-intervallinux,can-disablewakeup-source