� ��7�83�(�3�xlnx,zynq-zc706xlnx,zynq-7000&Xilinx ZC706 boardcpuscpu@0arm,cortex-a9,cpu8<C�Q] ,+B@B@ncpu@1arm,cortex-a9,cpu8<nfpga-full fpga-regionvpmu@f8891000arm,cortex-a9-pmu��8����0fixedregulatorregulator-fixed�VCCPINT�B@�B@��nreplicator arm,coresight-static-replicator<./apb_pclkdbg_trcdbg_apbout-portsport@08endpointnport@18endpointnin-portsportendpointnaxi simple-bus�adc@f8007100xlnx,zynq-xadc-1.00.a8�q  ��< can@e0008000xlnx,zynq-can-1.0 #disabled<$ can_clkpclk8�� ��*@8@can@e0009000xlnx,zynq-can-1.0 #disabled<% can_clkpclk8�� �3�*@8@gpio@e000a000xlnx,zynq-gpio-1.0F<*Rbw� �8���default�i2c@e0004000cdns,i2c-r1p10#okay<&� ���8�@�default� i2c-mux@74 nxp,pca95488ti2c@08clock-generator@5d� silabs,si570�28]� P/���� i2c@18hdmi-tx@39 adi,adv751189��yuv4221x%evenlyi2c@28eeprom@54 atmel,24c088Ti2c@38gpio@21 ti,tca64168!RFi2c@48rtc@51 nxp,pcf85638Qi2c@78ucd90120@65 ti,ucd901208ei2c@e0005000cdns,i2c-r1p10 #disabled<'� �0��8�Pinterrupt-controller@f8f01000arm,cortex-a9-gicwb8����ncache-controller@f8f02000arm,pl310-cache8��  � = N^lmemory-controller@f8006000xlnx,zynq-ddrc-a058�`serial@e0000000xlnx,xuartpscdns,uart-r1p8 #disabled<(uart_clkpclk8� �serial@e0001000xlnx,xuartpscdns,uart-r1p8#okay<)uart_clkpclk8� �2�default� spi@e0006000xlnx,zynq-spi-r1p68�` #disabled� �<" ref_clkpclkspi@e0007000xlnx,zynq-spi-r1p68�p #disabled� �1<# ref_clkpclkspi@e000d000xlnx,zynq-qspi-1.08��� �< + ref_clkpclk #disabledethernet@e000b000xlnx,zynq-gemcdns,gem8��#okay �< pclkhclktx_clk xrgmii-id� �default� ethernet-phy@78 ,ethernet-phyn ethernet@e000c000xlnx,zynq-gemcdns,gem8�� #disabled �-<pclkhclktx_clkmemory-controller@e000e000!arm,pl353-smc-r2p1arm,primecell8�� #disabledmemclkapb_pclk< ,0���nand-controller@0,0arm,pl353-nand-r2p1 8 #disabledmmc@e0100000arasan,sdhci-8.9a#okayclk_xinclk_ahb< � �8��default� mmc@e0101000arasan,sdhci-8.9a #disabledclk_xinclk_ahb<!� �/8�slcr@f8000000!xlnx,zynq-slcrsysconsimple-mfd8�nclkc@100�xlnx,ps7-clkc�j�armpllddrplliopllcpu_6or4xcpu_3or2xcpu_2xcpu_1xddr2xddr3xdcilqspismcpcapgem0gem1fclk0fclk1fclk2fclk3can0can1sdio0sdio1uart0uart1spi0spi1dmausb0_aperusb1_apergem0_apergem1_apersdio0_apersdio1_aperspi0_aperspi1_apercan0_apercan1_aperi2c0_aperi2c1_aperuart0_aperuart1_apergpio_aperlqspi_apersmc_aperswdtdbg_trcdbg_apb8���Unrstc@200xlnx,zynq-reset8H��pinctrl@700xlnx,pinctrl-zynq8�gem0-defaultn mux �ethernet0�ethernet0_0_grpconf�ethernet0_0_grp��conf-rx$�MIO22MIO23MIO24MIO25MIO26MIO27�conf-tx$�MIO16MIO17MIO18MIO19MIO20MIO21!2mux-mdio�mdio0 �mdio0_0_grpconf-mdio �mdio0_0_grp��2gpio0-defaultnmux�gpio0&�gpio0_7_grpgpio0_46_grpgpio0_47_grpconf&�gpio0_7_grpgpio0_46_grpgpio0_47_grp��conf-pull-up �MIO46MIO47?conf-pull-none�MIO72i2c0-defaultn mux �i2c0_10_grp�i2c0conf �i2c0_10_grp?��sdhci0-defaultn mux �sdio0_2_grp�sdio0conf �sdio0_2_grp��2mux-cd �gpio0_14_grp �sdio0_cdconf-cd �gpio0_14_grp�?��mux-wp �gpio0_15_grp �sdio0_wpconf-wp �gpio0_15_grp�?��uart1-defaultn mux �uart1_10_grp�uart1conf �uart1_10_grp��conf-rx�MIO49�conf-tx�MIO482usb0-defaultnmux �usb0_0_grp�usb0conf �usb0_0_grp��conf-rx�MIO29MIO31MIO36�conf-tx6�MIO28MIO30MIO32MIO33MIO34MIO35MIO37MIO38MIO392dma-controller@f8003000arm,pl330arm,primecell8�0�l� ()*+L< apb_pclkdevcfg@f8007000xlnx,zynq-devcfg-1.08�p� �< ref_clk�ntimer@f8f00200arm,cortex-a9-global-timer8��  � �<timer@f8001000�$�    cdns,ttc<8�timer@f8002000�$�%&' cdns,ttc<8� timer@f8f00600� � arm,cortex-a9-twd-timer8�� <usb@e0002000"xlnx,zynq-usb-2.20achipidea,usb2#okay<� �8� Wulpi`hosth�default�usb@e0003000"xlnx,zynq-usb-2.20achipidea,usb2 #disabled<� �,8�0Wulpiwatchdog@f8005000<-cdns,wdt-r1p2� � 8�Pp etb@f8801000"arm,coresight-etb10arm,primecell8��<./apb_pclkdbg_trcdbg_apbin-portsportendpointntpiu@f8803000!arm,coresight-tpiuarm,primecell8��0<./apb_pclkdbg_trcdbg_apbin-portsportendpointnfunnel@f8804000*arm,coresight-static-funnelarm,primecell8��@<./apb_pclkdbg_trcdbg_apbout-portsportendpointnin-portsport@08endpointnport@18endpointnport@28endpointptm@f889c000"arm,coresight-etm3xarm,primecell8���<./apb_pclkdbg_trcdbg_apb|out-portsportendpointnptm@f889d000"arm,coresight-etm3xarm,primecell8���<./apb_pclkdbg_trcdbg_apb|out-portsportendpointnaliases�/axi/ethernet@e000b000�/axi/i2c@e0004000�/axi/serial@e0001000�/axi/mmc@e0100000memory@0,memory8@chosen��serial0:115200n8phy0usb-nop-xceiv�n #address-cells#size-cellscompatiblemodeldevice_typeregclocksclock-latencycpu0-supplyoperating-pointsphandlefpga-mgrrangesinterruptsinterrupt-parentregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onclock-namesremote-endpointstatustx-fifo-depthrx-fifo-depth#gpio-cellsgpio-controllerinterrupt-controller#interrupt-cellspinctrl-namespinctrl-0clock-frequency#clock-cellstemperature-stabilityfactory-foutadi,input-depthadi,input-colorspaceadi,input-clockadi,input-styleadi,input-justificationarm,data-latencyarm,tag-latencycache-unifiedcache-levelphy-modephy-handlefclk-enableclock-output-namesps-clk-frequency#reset-cellssysconfunctiongroupsslew-rateio-standardpinsbias-high-impedancelow-power-disablelow-power-enablebias-disablebias-pull-up#dma-cellsphy_typedr_modeusb-phytimeout-seccpuethernet0i2c0serial0mmc0bootargsstdout-path#phy-cells