D8(Lgoogle,tentacruel-sku262151google,tentacruel-sku262150google,tentacruel-sku262149google,tentacruel-sku262148google,tentacruelmediatek,mt8186 +7Google Tentacruel board =convertiblealiasesJ/soc/ovl@14005000O/soc/ovl@14006000W/soc/rdma@14007000]/soc/rdma@1401f000c/soc/i2c@11007000h/soc/i2c@11008000m/soc/i2c@11009000r/soc/i2c@1100f000w/soc/i2c@11016000|/soc/mmc@11230000/soc/mmc@11240000/soc/serial@11002000/soc/i2c@11011000ccimediatek,mt8186-ccicciintermediate"opp-table-ccioperating-points-v2opp-500000000e 'opp-560000000!` Lopp-612000000$za opp-682000000(~  opp-752000000,Ҝ YF opp-8220000000  opp-8750000004'p  opp-9270000007@ 5 opp-980000000:i ~>opp-1050000000> opp-1120000000B )$opp-1155000000D opp-1190000000F opp-1260000000K~opp-1330000000OF0)opp-1400000000SrNRopp-table-cluster0operating-points-v2opp-500000000e 'opp-774000000."M Lopp-8750000004'p `opp-975000000:Q  opp-1075000000@2 q opp-1175000000F  X opp-1275000000K 5 opp-1375000000Q  opp-1500000000Yh/ opp-1618000000`p Yopp-1666000000cM$ opp-1733000000gK{@Hopp-1800000000kI~opp-1866000000o8opp-1933000000s7=@Zopp-2000000000w5Ropp-table-cluster1operating-points-v2#opp-774000000."M Lopp-8350000001 opp-9190000006 opp-1002000000;N YF opp-1085000000@@ X opp-1169000000E@ 5 opp-1308000000M  opp-1419000000T8 Y opp-1530000000[1 topp-1670000000c-Zopp-1733000000gK{@opp-1796000000k sopp-1860000000nYԼopp-1923000000r6dopp-1986000000v_vopp-2050000000z0cpus+cpu-mapcluster0core0core1core2core3core4core5core6core7cpu@0cpuarm,cortex-a55 psciw5cpuintermediate.TH~[ kx@@!"cpu@100cpuarm,cortex-a55 psciw5cpuintermediate.TH~[ kx@@!"cpu@200cpuarm,cortex-a55 psciw5cpuintermediate.TH~[ kx@@!"cpu@300cpuarm,cortex-a55 psciw5cpuintermediate.TH~[ kx@@!"cpu@400cpuarm,cortex-a55 psciw5cpuintermediate.TH~[ kx@@!"cpu@500cpuarm,cortex-a55 psciw5cpuintermediate.TH~[ kx@@!"cpu@600cpuarm,cortex-a76 psciz0cpuintermediate#.OH[$%kx@@&"'cpu@700cpuarm,cortex-a76 psciz0cpuintermediate#.OH[$%kx@@&"'idle-statespscicpu-retention-larm,idle-state%26dF@cpu-retention-barm,idle-state%26dFx$cpu-off-larm,idle-state%d6F4 cpu-off-barm,idle-state%d6Fl%l2-cache0cacheWmz@(c!l2-cache1cacheWmz@(c&l3-cachecacheWmz@c(fixed-factor-clock-13mfixed-factor-clockq)~clk13m=oscillator-26m fixed-clockqclk26m)oscillator-32k fixed-clockqclk32kopp-table-gpuoperating-points-v2wopp-299000000` Xopp-332000000 hopp-366000000з <opp-400000000ׄ Ҧopp-434000000P zopp-484000000A 4Nopp-535000000s }opp-586000000" `opp-637000000%@ 4opp-690000000)  @opp-743000000,IG opp-796000000/q opp-8500000002 5opp-900000000-35 Popp-900000000-45 |opp-900000000-55  opp-950000000-38ـ opp-950000000-48ـ Yopp-950000000-58ـ P opp-1000000000-3;~opp-1000000000-4; topp-1000000000-5; Y pmu-a55arm,cortex-a55-pmu *pmu-a76arm,cortex-a76-pmu +psci arm,psci-1.0smctimerarm,armv8-timer @   soc+ simple-businterrupt-controller@c000000 arm,gic-v3       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(TP)EN_PP1000_EDPBRDGEN_PP1800_EDPBRDGEN_PP3300_EDPBRDGUART_GSC_TX_AP_RXUART_AP_TX_GSC_RXUART_DBGCON_TX_ADSP_RXUART_ADSP_TX_DBGCON_RXEN_PP1000_DPBRDGTCHSCR_REPORT_DISABLEEN_PP3300_DPBRDGEN_PP1800_DPBRDGSPI_AP_CLK_ECSPI_AP_CS_EC_LSPI_AP_DO_EC_DISPI_AP_DI_EC_DOSPI_AP_CLK_GSCSPI_AP_CS_GSC_LSPI_AP_DO_GSC_DISPI_AP_DI_GSC_DOUART_DBGCON_TX_SCP_RXUART_SCP_TX_DBGCON_RXEN_PP1200_CAM_XEN_PP2800A_VCM_XEN_PP2800A_UCAM_XEN_PP2800A_WCAM_XWLAN_MODULE_RST_LEN_PP1200_UCAM_XI2S1_HP_DOI2S1_HP_BCKI2S1_HP_LRCKI2S1_HP_MCKTCHSCR_RST_1V8_LSPI_AP_CLK_ROMSPI_AP_CS_ROM_LSPI_AP_DO_ROM_DISPI_AP_DI_ROM_DONCNCEMMC_STRBEMMC_CLKEMMC_CMDEMMC_RST_LEMMC_DATA0EMMC_DATA1EMMC_DATA2EMMC_DATA3EMMC_DATA4EMMC_DATA5EMMC_DATA6EMMC_DATA7AP_KPCOL0NCNCNCTPSDIO_CLKSDIO_CMDSDIO_DATA0SDIO_DATA1SDIO_DATA2SDIO_DATA3NCNCNCNCNCNCEDPBRDG_PWRENBL_PWM_1V8EDPBRDG_RST_LMIPI_DPI_CLKMIPI_DPI_VSYNCMIPI_DPI_HSYNCMIPI_DPI_DEMIPI_DPI_D0MIPI_DPI_D1MIPI_DPI_D2MIPI_DPI_D3MIPI_DPI_D4MIPI_DPI_D5MIPI_DPI_D6MIPI_DPI_DA7MIPI_DPI_D8MIPI_DPI_D9MIPI_DPI_D10MIPI_DPI_D11PCM_BT_CLKPCM_BT_SYNCPCM_BT_DIPCM_BT_DOJTAG_TMS_TPJTAG_TCK_TPJTAG_TDI_TPJTAG_TDO_TPJTAG_TRSTN_TPCLK_24M_WCAMCLK_24M_UCAMUCAM_DET_ODLAP_I2C_EDPBRDG_SCL_1V8AP_I2C_EDPBRDG_SDA_1V8AP_I2C_TCHSCR_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_TCHPAD_SCL_1V8AP_I2C_TCHPAD_SDA_1V8AP_I2C_DPBRDG_SCL_1V8AP_I2C_DPBRDG_SDA_1V8AP_I2C_WLAN_SCL_1V8AP_I2C_WLAN_SDA_1V8AP_I2C_AUD_SCL_1V8AP_I2C_AUD_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_UCAM_SDA_1V8AP_I2C_UCAM_SCL_1V8AP_I2C_UCAM_SDA_1V8AP_I2C_WCAM_SCL_1V8AP_I2C_WCAM_SDA_1V8SCP_I2C_SENSOR_SCL_1V8SCP_I2C_SENSOR_SDA_1V8AP_EC_WARM_RST_REQAP_XHCI_INIT_DONEUSB3_HUB_RST_LEN_SPKRBEEP_ONAP_EDP_BKLTENEN_PP3300_DISP_XEN_PP3300_SDBRDG_XBT_KILL_1V8_LWIFI_KILL_1V8_LPWRAP_SPI0_CSNPWRAP_SPI0_CKPWRAP_SPI0_MOPWRAP_SPI0_MISRCLKENA0SRCLKENA1SCP_VREQ_VAOAP_RTC_CLK32KAP_PMIC_WDTRST_LAUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_CLK_MISOAUD_SYNC_MISOAUD_DAT_MISO0AUD_DAT_MISO1NCNCDPBRDG_PWRENDPBRDG_RST_LLTE_W_DISABLE_LLTE_SAR_DETECT_LEN_PP3300_LTE_XLTE_PWR_OFF_LLTE_RESET_LTPTP,aud-clk-mosi-off-pinspins-clk-syncaud-clk-mosi-on-pinspins-clk-syncaud-clk-miso-off-pinspins-clk-syncaud-clk-miso-on-pinspins-clk-syncaud-dat-mosi-off-pinspins-dataud-dat-mosi-on-pinspins-dataud-dat-miso-off-pinspins-dataud-dat-miso-on-pinspins-dataud-gpio-i2s0-off-pinspins-sdataaud-gpio-i2s0-on-pinspins-sdataaud-gpio-i2s-off-pinspins-clk-sdata89:;aud-gpio-i2s1-on-pinspins-clk-sdata89:;aud-gpio-i2s2-off-pinspins-cmd-dataud-gpio-i2s2-on-pinspins-clkaud-gpio-i2s3-off-pinspins-sdataaud-gpio-i2s3-on-pinspins-sdataaud-gpio-pcm-off-pinspins-clk-sdatastuvaud-gpio-pcm-on-pinspins-clk-sdatastuvaud-gpio-dmic-sec-pinspinsbt-reset-pinsqpins-bt-resetdpi-sleep-pins|pins-cmd-dat@ghijklmnopqredfc dpi-default-pins{pins-cmd-dat@ghijklmnopqredfc cros-ec-int-pinsdpins-ec-ap-int-odl edp-panel-fixed-pinspins-vreg-enen-pp1800-dpbrdg-pinspins-vreg-en'gsc-int-pinsfpins-gsc-ap-int-odli2c0-pinsGpins-busi2c1-pinsPpins-busi2c2-pinsSpins-busi2c3-pinsUpins-busi2c5-pins]pins-busit6505-pinsVpins-hpd pins-intpins-resetmmc0-default-pinsjpins-clkDfpins-cmd-dat$GHIJKLMNEepins-rstFemmc0-uhs-pinskpins-clkDfpins-cmd-dat$GHIJKLMNEepins-dsCfpins-rstFemmc1-default-pinsmpins-clkTfpins-cmd-datVWXYUemmc1-uhs-pinsnpins-clkTfpins-cmd-datVWXYUemmc1-eint-pinsopins-dat1Wenor-default-pinsEpins-clk-dat ?=@pins-cs-dat >ABpen-eject-pinspinsdisp-pwm-pinsbpinsart1019p-default-pinspins-sdbscp-default-pins>pins-scp-uart01spi1-pinscpins-bus()*+spi2-pinsepins-bus,-./spmi-pinspins-bustouchscreen-pinsQpins-irq pins-reset<pins-report-sw%trackpad-default-pinsTpins-int-n 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Sadc@11001000.mediatek,mt8186-auxadcmediatek,mt8173-auxadc */"mainserial@11002000*mediatek,mt8186-uartmediatek,mt6577-uart  p )/ baudbusokayserial@11003000*mediatek,mt8186-uartmediatek,mt6577-uart 0q )/ baudbus disabledi2c@11007000mediatek,mt8186-i2c  p iF/' maindma~+okaydefaultGedp-bridge@8parade,ps8640 defaultH <,` L,bXIeJports+port@0 endpointrKport@1 endpointrLOaux-buspanel edp-panelMNportendpointrOLi2c@11008000mediatek,mt8186-i2c   jF/' maindma~+okaydefaultP'touchscreen@10 hid-over-i2c  _, defaultQ tRi2c@11009000mediatek,mt8186-i2c   kF/' maindma~+okaydefaultST'trackpad@15 hid-over-i2c  _, tRi2c@1100f000mediatek,mt8186-i2c   lF/' maindma~+okaydefaultUdp-bridge@5c ite,it6505 \ _,defaultVWX L,ports+port@0 endpointрrY}port@1 i2c@11011000mediatek,mt8186-i2c   mF/' maindma~+okaydefaultZproximity@28semtech,sx9324 (* _,default[t\"\i2c@11016000mediatek,mt8186-i2c  ` bF/' maindma~+okaydefault]codec@1arealtek,rt5682s  _,.\:\G\V^di2c@1100d000mediatek,mt8186-i2c   cF/' maindma~+ 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audiosysokayusb@11201000#mediatek,mt8186-mtu3mediatek,mtu3   - > @macippc(-/=/3//>$sys_ckref_ckmcu_ckdma_ckxhci_ck/ h B+okayusb@11200000'mediatek,mt8186-xhcimediatek,mtk-xhci  @mac(-/=/3//>$sys_ckref_ckmcu_ckdma_ckxhci_ck& i okay Rmmc@11230000(mediatek,mt8186-mmcmediatek,mt8183-mmc  # - //U/sourcehclksource_cgcryptodv- okaydefaultstate_uhsj k     ' 6 E R X ` q  l \mmc@11240000(mediatek,mt8186-mmcmediatek,mt8183-mmc  $-//Vsourcehclksource_cgv--ookaydefaultstate_uhsstate_eintm n o msdcsdio_wakeup _e,W+         R  R \ pbluetooth@2mediatek,mt7921s-bluetooth defaultq L,usb@11281000#mediatek,mt8186-mtu3mediatek,mtu3  (-(> @macippc$/B/?/7)/@$sys_ckref_ckmcu_ckdma_ckxhci_ckK rs B+okayusb@11280000'mediatek,mt8186-xhcimediatek,mtk-xhci (@mac$/B/?/7)/@$sys_ckref_ckmcu_ckdma_ckxhci_ckD i$okay tt-phy@11c80000.mediatek,mt8186-tphymediatek,generic-tphy-v2+okayusb-phy@0 )ref +rusb-phy@700  )ref +st-phy@11ca0000.mediatek,mt8186-tphymediatek,generic-tphy-v2+okayusb-phy@0 )ref + 6hefuse@11cb0000%mediatek,mt8186-efusemediatek,efuse +lvts1-calib@1cc _lvts2-calib@2f8 `calib@550 PPagpu-speedbin@59c  Fvsocinfo-data1@7a0 dsi-phy@11cc0000mediatek,mt8183-mipi-tx )q + mipi_tx0_pllokay~clock-controller@13000000mediatek,mt8186-mfgsys qugpu@13040000&mediatek,mt8186-maliarm,mali-bifrost @u0 jobmmugpu BB Kcore0core1zv speed-binw.Ookay ^0syscon@14000000mediatek,mt8186-mmsyssyscon q3xx jx1mutex@14001000mediatek,mt8186-disp-mutex 1' jx  Bsmi@14002000mediatek,mt8186-smi-common   1111apbsmigals0gals1 Bysmi@14003000mediatek,mt8186-smi-larb 011apbsmi  y Bsmi@14004000mediatek,mt8186-smi-larb @11apbsmi  y Bovl@140050002mediatek,mt8186-disp-ovlmediatek,mt8192-disp-ovl P1) z jxP Bovl@140060008mediatek,mt8186-disp-ovl-2lmediatek,mt8192-disp-ovl-2l `1* z! jx` Brdma@140070004mediatek,mt8186-disp-rdmamediatek,mt8183-disp-rdma p1+ z" jxp Bcolor@140090006mediatek,mt8186-disp-colormediatek,mt8173-disp-color 1 - jx Bdpi@1400a000mediatek,mt8186-dpi -;1 pixelenginepllv-;-j5 B disableddefaultsleep{ |portendpointr}Yccorr@1400b0006mediatek,mt8186-disp-ccorrmediatek,mt8192-disp-ccorr 1. jx Baal@1400c0002mediatek,mt8186-disp-aalmediatek,mt8183-disp-aal 10 jx Bgamma@1400d0006mediatek,mt8186-disp-gammamediatek,mt8183-disp-gamma 1 1 jx Bpostmask@1400e000<mediatek,mt8186-disp-postmaskmediatek,mt8192-disp-postmask 1 2 jx Bdither@1400f0008mediatek,mt8186-disp-dithermediatek,mt8183-disp-dither 13 jx Bdsi@14013000mediatek,mt8186-dsi 011~enginedigitalhs7 Bs1 ~ dphyokayportendpointrKiommu@14016000mediatek,mt8186-iommu-mm `1bclk98  B zrdma@1401f0004mediatek,mt8186-disp-rdmamediatek,mt8183-disp-rdma 14 z  jx Bclock-controller@14020000mediatek,mt8186-wpesys q7smi@14023000mediatek,mt8186-smi-larb 077apbsmi  y Bclock-controller@15020000mediatek,mt8186-imgsys1 q4smi@1502e000mediatek,mt8186-smi-larb 44apbsmi  y Bclock-controller@15820000mediatek,mt8186-imgsys2 qsmi@1582e000mediatek,mt8186-smi-larb 4apbsmi  y Bvideo-decoder@16000000mediatek,mt8186-vcodec-dec +@ z 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Bclock-controller@1c000000mediatek,mt8186-ipesys q5smi@1c00f000mediatek,mt8186-smi-larb 55apbsmi  y B smi@1c10f000mediatek,mt8186-smi-larb 55apbsmi  y B thermal-zonescpu-little0-thermal   tripstrip-alert0 "L .Epassivetrip-alert1 "s .Ehottrip-crit " . Ecriticalcooling-mapsmap0 9H >cpu-little1-thermal   tripstrip-alert0 "L .Epassivetrip-alert1 "s .Ehottrip-crit " . Ecriticalcooling-mapsmap0 9H >cpu-little2-thermal   tripstrip-alert0 "L .Epassivetrip-alert1 "s .Ehottrip-crit " . Ecriticalcooling-mapsmap0 9H >cam-thermal   tripstrip-alert0 "L .Epassivetrip-alert1 "s .Ehottrip-crit " . Ecriticalnna-thermal   tripstrip-alert0 "L .Epassivetrip-alert1 "s .Ehottrip-crit " . Ecriticaladsp-thermal   tripstrip-alert0 "L .Epassivetrip-alert1 "s .Ehottrip-crit " . Ecriticalgpu-thermal   tripstrip-alert0 "L .Epassivetrip-alert1 "s .Ehottrip-crit " . Ecriticalcooling-mapsmap0 9 >cpu-big0-thermal  d tripstrip-alert0 "L .Epassivetrip-alert1 "s .Ehottrip-crit " . Ecriticalcooling-mapsmap0 9 >cpu-big1-thermal  d tripstrip-alert0 "L .Epassivetrip-alert1 "s .Ehottrip-crit " . Ecriticalcooling-mapsmap0 9 >chosen Mserial0:115200n8memory@40000000memory @backlight-lcd0pwm-backlight Y  ^, k } @Nbt-sco linux,bt-scodmic-codec dmic-codec  2gpio-keys gpio-keysdefaultpen-insert-switch Pen Insert F,   regulator-pp1800-dpbrdg-dxregulator-fixeddefault F,'pp1800_dpbrdg_dx  \Xregulator-pp3300-disp-xregulator-fixeddefault F,pp3300_disp_x   ^Mregulator-pp3300-ldo-z5regulator-fixedpp3300_ldo_z5. 2Z2Z regulator-pp3300-s3regulator-fixed pp3300_s3.  ^Rregulator-pp3300-z2regulator-fixed pp3300_z2. 2Z2Z ^regulator-pp4200-z2regulator-fixed pp4200_z2. @@@@ 9regulator-pp5000-z2regulator-fixed pp5000_z2. LK@LK@ regulator-ppvar-sysregulator-fixed ppvar_sys. reserved-memory+memory@61000000shared-dma-pool a *Cmemory@60000000shared-dma-pool ` *Dmemory@50000000shared-dma-pool P  *?sound,mediatek,mt8186-mt6366-rt1019-rt5682s-soundCaud_clk_mosi_offaud_clk_mosi_onaud_clk_miso_offaud_clk_miso_onaud_dat_miso_offaud_dat_miso_onaud_dat_mosi_offaud_dat_mosi_onaud_gpio_i2s0_offaud_gpio_i2s0_onaud_gpio_i2s1_offaud_gpio_i2s1_onaud_gpio_i2s2_offaud_gpio_i2s2_onaud_gpio_i2s3_offaud_gpio_i2s3_onaud_gpio_pcm_offaud_gpio_pcm_onaud_gpio_dmic_sec   1 ; E O Y c m w          I HeadphoneHPOLHeadphoneHPORIN1PHeadset MicSpeakersSpeakerHDMI1TXhs-playback-dai-linkI2S0i2scpucodec3hs-capture-dai-linkI2S1i2scpucodec3spk-share-dai-linkI2S2cpuspk-hdmi-playback-dai-linkI2S3i2scpucodec3speaker-codecrealtek,rt1019pdefault =,regulator-usb-p1-vbusregulator-fixed G,vbus1LK@LK@  twifi-pwrseqmmc-pwrseq-simpledefault2 L,6pwifi-wakeup gpio-keysdefaultwowlan-event Wake on WiFi F,  compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeovl0ovl-2l0rdma0rdma1i2c0i2c1i2c2i2c3i2c5mmc0mmc1serial0i2c4clocksclock-namesoperating-points-v2proc-supplyphandleopp-sharedopp-hzopp-microvoltrequired-oppscpudevice_typeregenable-methodclock-frequencydynamic-power-coefficientcapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsmediatek,ccientry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-divclock-multclock-output-namesopp-supported-hwinterruptsdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxinput-enablebias-pull-downinput-schmitt-enablebias-disableoutput-lowdrive-strengthoutput-highbias-pull-up#power-domain-cellsdomain-supplymediatek,infracfgmediatek,disable-extrstmediatek,reset-by-toprguinterrupts-extendedAvdd-supplymediatek,dmic-modevsys-ldo1-supplyvsys-ldo2-supplyvsys-ldo3-supplyvsys-vcore-supplyvsys-vdram1-supplyvsys-vgpu-supplyvsys-vmodem-supplyvsys-vpa-supplyvsys-vproc11-supplyvsys-vproc12-supplyvsys-vs1-supplyvsys-vs2-supplyvs1-ldo1-supplyvs2-ldo1-supplyvs2-ldo2-supplyvs2-ldo3-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-allowed-modesregulator-always-onregulator-coupled-withregulator-coupled-max-spreadassigned-clocksassigned-clock-parentsstatus#mbox-cellspinctrl-namespinctrl-0firmware-namememory-regionmediatek,rpmsg-namembox-namesmboxespower-domainsspi-max-frequency#io-channel-cellspowerdown-gpiosreset-gpiosvdd12-supplyvdd33-supplyremote-endpointpower-supplybacklighti2c-scl-internal-delay-nspost-power-on-delay-mshid-descr-addrwakeup-source#sound-dai-cellsovdd-supplypwr18-supplylink-frequenciessvdd-supplyAVDD-supplyDBVDD-supplyLDO1-IN-supplyMICVDD-supplyrealtek,jd-srcresetsnvmem-cellsnvmem-cell-names#thermal-sensor-cellsreset-names#pwm-cellsmediatek,pad-selectgoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countlabelpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapcs-gpiosmediatek,apmixedsysmediatek,topckgenphysmediatek,syscon-wakeupvbus-supplypinctrl-1bus-widthnon-removablecap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqeno-sdno-sdiocap-mmc-hw-reseths400-ds-delaymediatek,hs400-ds-dly3vmmc-supplyvqmmc-supplypinctrl-2interrupt-namescap-sd-highspeedsd-uhs-sdr104sd-uhs-sdr50keep-power-in-suspendcap-sdio-irqno-mmcmmc-pwrseq#phy-cellsmediatek,discthbitspower-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,larb-idmediatek,smiiommusphy-namesmediatek,larbs#iommu-cellsmediatek,scppolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathpwmsenable-gpiosbrightness-levelsnum-interpolated-stepsdefault-brightness-levelnum-channelswakeup-delay-mswakeup-event-actionlinux,codelinux,input-typeenable-active-highvin-supplyregulator-boot-onno-mappinctrl-3pinctrl-4pinctrl-5pinctrl-6pinctrl-7pinctrl-8pinctrl-9pinctrl-10pinctrl-11pinctrl-12pinctrl-13pinctrl-14pinctrl-15pinctrl-16pinctrl-17pinctrl-18mediatek,adspmediatek,platformaudio-routinglink-namedai-formatmediatek,clk-providersound-daisdb-gpiosgpio