Ð þíd8€(äH<Amazon's Annapurna Labs Alpine v3 Evaluation Platform (EVP),amazon,al-alpine-v3-evpamazon,al-alpine-v3"1cpus"1cpu@0=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@1=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@2=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@3=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@100=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@101=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@102=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@103=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@200=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@201=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@202=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@203=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@300=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@301=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@302=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cpu@303=cpuarm,cortex-a72IMpsci[€h@z‡À”@¦³cache-0cache] j@|ÄÐÞcache-100cache] j@|ÄÐÞcache-200cache] j@|ÄÐÞcache-300cache] j@|ÄÐÞreserved-memory"1æsecmon@0Iípsci arm,psci-0.2Tsmctimerarm,armv8-timer0ô   pmuarm,cortex-a72-pmu ôsoc simple-bus"1æinterrupt-controller@f0800000 arm,gic-v3ÿPIð€ð  ð ðð  ô Þpcie@fbd00000pci-host-ecam-generic=pci1"ÿIûÐ%ø8@9H:P;X<`=h>p?x@æþþFPmsix@fbe00000al,alpine-msixIûà[jPz¿Þio-fabric@fc000000 simple-bus"1æüserial@1883000 ns16550aIˆ0 ôŠš¤±okayserial@1884000 ns16550aIˆ@ ôŠš¤ ±disabledserial@1885000 ns16550aIˆP ôŠš¤ ±disabledserial@1886000 ns16550aIˆ` ôŠš¤ ±disabledaliases'¸/soc/io-fabric@fc000000/serial@1883000'À/soc/io-fabric@fc000000/serial@1884000'È/soc/io-fabric@fc000000/serial@1885000'Ð/soc/io-fabric@fc000000/serial@1886000chosenØserial0:115200n8 modelcompatibleinterrupt-parent#address-cells#size-cellsdevice_typeregenable-methodd-cache-sized-cache-line-sized-cache-setsi-cache-sizei-cache-line-sizei-cache-setsnext-level-cachecache-levelcache-unifiedphandlerangesno-mapinterrupts#interrupt-cellsinterrupt-controllerinterrupt-map-maskinterrupt-mapbus-rangemsi-parentmsi-controlleral,msi-base-spial,msi-num-spisclock-frequencyreg-shiftreg-io-widthstatusserial0serial1serial2serial3stdout-path