8(9X$mediatek,mt8192-evbmediatek,mt8192 +!7MediaTek MT8192 evaluation boardaliases=/soc/ovl@14005000B/soc/ovl@14006000J/soc/ovl@14014000R/soc/rdma@14007000X/soc/rdma@14015000^/soc/serial@11002000fixed-factor-clock-13mfixed-factor-clockfszclk13m$oscillator0 fixed-clockfclk26moscillator1 fixed-clockfclk32kcpus+cpu@0cpuarm,cortex-a55psciec3@@!@3@Qex cpu@100cpuarm,cortex-a55psciec3@@!@3@Qex cpu@200cpuarm,cortex-a55psciec3@@!@3@Qex cpu@300cpuarm,cortex-a55psciec3@@!@3@Qex cpu@400cpuarm,cortex-a76pscif@!@3@ Qexcpu@500cpuarm,cortex-a76pscif@!@3@ Qexcpu@600cpuarm,cortex-a76pscif@!@3@ Qexcpu@700cpuarm,cortex-a76pscif@!@3@ Qexcpu-mapcluster0core0 core1 core2 core3 core4core5core6core7l2-cache0cache@ @l2-cache1cache@ @ l3-cachecache @ idle-statespscicpu-retention-larm,idle-state7 cpu-retention-barm,idle-state#cpu-off-larm,idle-state<\cpu-off-barm,idle-state( pmu-a55arm,cortex-a55-pmu  pmu-a76arm,cortex-a76-pmu  psci arm,psci-1.0smctimerarm,armv8-timer @    ]@opp-table-0operating-points-v25opp-358000000"V) @*opp-399000000"A) popp-440000000"9) opp-482000000") Ҧopp-523000000",X) zopp-564000000"!) 4Nopp-605000000"$@) e"opp-647000000"&o) opp-688000000") ) opp-724000000"+']) opp-748000000",) @opp-772000000".) qopp-795000000"/b) opp-819000000"0) Xopp-843000000"2?() ,opp-866000000"3) 5soc+ simple-bus7;performance-controller@11bc10mediatek,cpufreq-hw  0 Binterrupt-controller@c000000 arm,gic-v3\m      ppi-partitionsinterrupt-partition-0 interrupt-partition-1syscon@10000000 mediatek,mt8192-topckgensysconfsyscon@10001000 mediatek,mt8192-infracfgsysconfsyscon@10003000mediatek,mt8192-pericfgsyscon0f*pinctrl@10005000mediatek,mt8192-pinctrlP]iocfg0iocfg_rmiocfg_bmiocfg_bliocfg_briocfg_lmiocfg_lbiocfg_rtiocfg_ltiocfg_tleint \syscon@10006000)mediatek,mt8192-scpsyssysconsimple-mfd`power-controller!mediatek,mt8192-power-controller+,power-domain@0s:/audioaudio1audio2power-domain@1sconnpower-domain@2s mfgalt+power-domain@3+power-domain@4power-domain@5power-domain@6power-domain@7power-domain@8power-domain@9 (s !dispdisp-0disp-1disp-2disp-3+power-domain@10 (sipeipe-0ipe-1ipe-2ipe-3power-domain@11 sispisp-0isp-1power-domain@12 sisp2isp2-0isp2-1power-domain@13 s mdpmdp-0power-domain@14s3 vencvenc-0power-domain@15 s4vdecvdec-0vdec-1vdec-2+power-domain@16svdec2-0vdec2-1vdec2-2power-domain@17(s   camcam-0cam-1cam-2cam-3+power-domain@18s! cam_rawa-0power-domain@19s" cam_rawb-0power-domain@20s# cam_rawc-0watchdog@10007000mediatek,mt8192-wdtp+syscon@1000c000"mediatek,mt8192-apmixedsyssysconf)timer@10017000,mediatek,mt8192-timermediatek,mt6765-timerp s$pwrap@10026000mediatek,mt6873-pwrap`pwrap s spiwrap#pmicmediatek,mt6359\adcmediatek,mt6359-auxadc:mt6359codecregulatorsbuck_vs1Lvs1[ 5s!buck_vgpu11Lvgpu11[s7 buck_vmodemLvmodem[s*buck_vpuLvpu[s7 buck_vcoreLvcore[s  buck_vs2Lvs2[ 5sjbuck_vpaLvpa[ s7,buck_vproc2Lvproc2[s7L buck_vproc1Lvproc1[s7L buck_vcore_sshub Lvcore_sshub[s7buck_vgpu11_sshub Lvgpu11_sshub[s7ldo_vaud18Lvaud18[w@sw@ldo_vsim1Lvsim1[s/M`ldo_vibrLvibr[Os2Zldo_vrf12Lvrf12[s ldo_vusbLvusb[-s-ldo_vsram_proc2 Lvsram_proc2[ sLldo_vio18Lvio18[sldo_vcamioLvcamio[sldo_vcn18Lvcn18[w@sw@ldo_vfe28Lvfe28[*s*xldo_vcn13Lvcn13[ s ldo_vcn33_1_bt Lvcn33_1_bt[*s5gldo_vcn33_1_wifi Lvcn33_1_wifi[*s5gldo_vaux18Lvaux18[w@sw@ldo_vsram_others Lvsram_others[ sldo_vefuseLvefuse[sldo_vxo22Lvxo22[w@s!ldo_vrfckLvrfck[`sldo_vrfck_1Lvrfck[sjldo_vbif28Lvbif28[*s*ldo_vio28Lvio28[*s2Zldo_vemcLvemc[,@ s2Zldo_vemc_1Lvemc[&%s2Zldo_vcn33_2_bt Lvcn33_2_bt[*s5gldo_vcn33_2_wifi Lvcn33_2_wifi[*s5gldo_va12Lva12[Os ldo_va09Lva09[ 5sOldo_vrf18Lvrf18[sPldo_vsram_md Lvsram_md[ s*ldo_vufsLvufs[sldo_vm18Lvm18[sldo_vbbckLvbbck[sOldo_vsram_proc1 Lvsram_proc1[ sLldo_vsim2Lvsim2[s/M`ldo_vsram_others_sshubLvsram_others_sshub[ smt6359rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt6873-spmi p pmifspmimsts8(pmif_sys_ckpmif_tmr_ckspmimst_clk_mux#mailbox@10228000mediatek,mt8192-gce"@ sgce6clock-controller@10720000mediatek,mt8192-scp_adsprffailserial@11002000*mediatek,mt8192-uartmediatek,mt6577-uart  m s baudbusokayserial@11003000*mediatek,mt8192-uartmediatek,mt6577-uart0 n s baudbus disabledclock-controller@11007000mediatek,mt8192-imp_iic_wrap_cpfspi@1100a000(mediatek,mt8192-spimediatek,mt6765-spi+ sMparent-clksel-clkspi-clk disabledthermal-sensor@1100b000mediatek,mt8192-lvts-ap  s %lvts-calib-data-1Ssvs@1100bc00mediatek,mt8192-svs s main&%(svs-calibration-datat-calibration-data5svs_rstpwm@1100e000mediatek,mt8183-disp-pwm As!8mainmm disabledspi@11010000(mediatek,mt8192-spimediatek,mt6765-spi+ sM<parent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8192-spimediatek,mt6765-spi+  sM>parent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8192-spimediatek,mt6765-spi+0 sM?parent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8192-spimediatek,mt6765-spi+ sMLparent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8192-spimediatek,mt6765-spi+ sMMparent-clksel-clkspi-clk disabledspi@1101d000(mediatek,mt8192-spimediatek,mt6765-spi+ sMmparent-clksel-clkspi-clk disabledspi@1101e000(mediatek,mt8192-spimediatek,mt6765-spi+ sMnparent-clksel-clkspi-clk disabledscp@10500000mediatek,mt8192-scp0Prpsramcfgl1tcm smain disabledIusb@11200000'mediatek,mt8192-xhcimediatek,mtk-xhci   > macippcLa`hostp'("##]] s7)R$sys_ckref_ckmcu_ckdma_ckxhci_cku * f disabledsyscon@11210000mediatek,mt8192-audsyssyscon! f-mt8192-afe-pcmmediatek,mt8192-audio + 5audiosys),s----------- - --------/:H/e0i+g,k;<=>?@ABCD7uaud_afe_clkaud_dac_clkaud_dac_predis_clkaud_adc_clkaud_adda6_adc_clkaud_apll22m_clkaud_apll24m_clkaud_apll1_tuner_clkaud_apll2_tuner_clkaud_tdm_clkaud_tml_clkaud_nleaud_dac_hires_clkaud_adc_hires_clkaud_adc_hires_tmlaud_adda6_adc_hires_clkaud_3rd_dac_clkaud_3rd_dac_predis_clkaud_3rd_dac_tmlaud_3rd_dac_hires_clkaud_infra_clkaud_infra_26m_clktop_mux_audiotop_mux_audio_inttop_mainpll_d4_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d4top_mux_aud_eng2top_apll2_d4top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s3_m_seltop_i2s4_m_seltop_i2s5_m_seltop_i2s6_m_seltop_i2s7_m_seltop_i2s8_m_seltop_i2s9_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div3top_apll12_div4top_apll12_divbtop_apll12_div5top_apll12_div6top_apll12_div7top_apll12_div8top_apll12_div9top_mux_audio_htop_clk26m_clkpcie@11230000mediatek,mt8192-pciepci#  pcie-mac+0s+'*j^\/pl_250mtl_26mtl_96mtl_32kperi_26mtop_133m)#Q 8;\`....interrupt-controller\.spi@11234000mediatek,mt8192-nor#@ s:w] spisfaxi:#+ disabledthermal-sensor@11278000mediatek,mt8192-lvts-mcu' s %lvts-calib-data-1Jefuse@11c10000%mediatek,mt8192-efusemediatek,efuse+socinfo-data1@44Dsocinfo-data2@50Pdata1@1c0X%calib@580h&i2c@11cb0000mediatek,mt8192-i2c !s ss/x maindmaz+ disabledclock-controller@11cb1000mediatek,mt8192-imp_iic_wrap_ef/i2c@11d00000mediatek,mt8192-i2c !v ws0x maindmaz+ disabledi2c@11d01000mediatek,mt8192-i2c !w xs0x maindmaz+ disabledi2c@11d02000mediatek,mt8192-i2c  !y ys0x maindmaz+ disabledclock-controller@11d03000mediatek,mt8192-imp_iic_wrap_s0f0i2c@11d20000mediatek,mt8192-i2c !q qs1x maindmaz+ disabledi2c@11d21000mediatek,mt8192-i2c !q rs1x maindmaz+ disabledi2c@11d22000mediatek,mt8192-i2c  !s ts1x maindmaz+ disabledclock-controller@11d23000 mediatek,mt8192-imp_iic_wrap_ws0f1i2c@11e00000mediatek,mt8192-i2c !u us2x maindmaz+ disabledclock-controller@11e01000mediatek,mt8192-imp_iic_wrap_wf2t-phy@11e40000.mediatek,mt8192-tphymediatek,generic-tphy-v2+;usb-phy@0sref'usb-phy@700 sref(dsi-phy@11e50000mediatek,mt8183-mipi-txs) f mipi_tx0_pll disabled9i2c@11f00000mediatek,mt8192-i2c !p ps3x maindmaz+ disabledi2c@11f01000mediatek,mt8192-i2c !u vs3x maindmaz+ disabledclock-controller@11f02000mediatek,mt8192-imp_iic_wrap_n f3clock-controller@11f10000mediatek,mt8192-msdc_topf4mmc@11f60000(mediatek,mt8192-mmcmediatek,mt8183-mmc  c8s4 444443sourcehclksource_cgsys_cgpclk_cgaxi_cgahb_cg disabledmmc@11f70000(mediatek,mt8192-mmcmediatek,mt8183-mmc  g8s4 444443sourcehclksource_cgsys_cgpclk_cgaxi_cgahb_cg disabledgpu@13000000)mediatek,mt8192-maliarm,mali-valhall-jm@0 mlk `jobmmugpus)(,,,,,core0core1core2core3core45 disabledclock-controller@13fbf000mediatek,mt8192-mfgcfgfsyscon@14000000mediatek,mt8192-mmsyssysconf+6626mutex@14001000mediatek,mt8192-disp-mutex s26J, smi@14002000mediatek,mt8192-smi-common  s apbsmigals0gals1, 7larb@14003000mediatek,mt8192-smi-larb0^o7sapbsmi, :larb@14004000mediatek,mt8192-smi-larb@^o7sapbsmi, ;ovl@14005000mediatek,mt8192-disp-ovlP s|88, 26Povl@14006000mediatek,mt8192-disp-ovl-2l` , s|8"8 26`rdma@140070004mediatek,mt8192-disp-rdmamediatek,mt8183-disp-rdmap s|8, 26pcolor@140090006mediatek,mt8192-disp-colormediatek,mt8173-disp-color , s26ccorr@1400a000mediatek,mt8192-disp-ccorr , s 26aal@1400b0002mediatek,mt8192-disp-aalmediatek,mt8183-disp-aal , s26gamma@1400c0006mediatek,mt8192-disp-gammamediatek,mt8183-disp-gamma , s 26postmask@1400d000mediatek,mt8192-disp-postmask , s 26dither@1400e0008mediatek,mt8192-disp-dithermediatek,mt8183-disp-dither , s 26dsi@14010000mediatek,mt8183-dsi  s 9enginedigitalhsp9dphy,  disabledportendpointovl@14014000mediatek,mt8192-disp-ovl-2l@  , s|8#8!26@rdma@140150004mediatek,mt8192-disp-rdmamediatek,mt8183-disp-rdmaP  , s|8%26Pdpi@14016000mediatek,mt8192-dpi` s!)pixelenginepll disabledm4u@1401d000mediatek,mt8192-m4u<:;<=>?@ABCDEFGH sbclk, 8clock-controller@15020000mediatek,mt8192-imgsysflarb@1502e000mediatek,mt8192-smi-larb^ o7sapbsmi, @clock-controller@15820000mediatek,mt8192-imgsys2flarb@1582e000mediatek,mt8192-smi-larb^ o7sapbsmi, Avideo-codec@16000000mediatek,mt8192-vcodec-decI|8+;`video-codec@10000mediatek,mtk-vcodec-lat @|88888888(s4Fselsoc-vdecsoc-latvdectop4#F,video-codec@25000mediatek,mtk-vcodec-coreP X|88888888888(s4Fselsoc-vdecsoc-latvdectop4#F,larb@1600d000mediatek,mt8192-smi-larb^o7sapbsmi,>clock-controller@1600f000mediatek,mt8192-vdecsys_socflarb@1602e000mediatek,mt8192-smi-larb^o7sapbsmi,=clock-controller@1602f000mediatek,mt8192-vdecsysfclock-controller@17000000mediatek,mt8192-vencsysflarb@17010000mediatek,mt8192-smi-larb^o7sapbsmi,?vcodec@17020000mediatek,mt8192-vcodec-enc X|88888888888 5I,s venc_sel3#Wclock-controller@1a000000mediatek,mt8192-camsysf larb@1a001000mediatek,mt8192-smi-larb^ o7s  apbsmi,Blarb@1a002000mediatek,mt8192-smi-larb ^o7s  apbsmi,Clarb@1a00f000mediatek,mt8192-smi-larb^o7s!!apbsmi,Dlarb@1a010000mediatek,mt8192-smi-larb^o7s""apbsmi,Elarb@1a011000mediatek,mt8192-smi-larb^o7s##apbsmi,Fclock-controller@1a04f000mediatek,mt8192-camsys_rawaf!clock-controller@1a06f000mediatek,mt8192-camsys_rawbf"clock-controller@1a08f000mediatek,mt8192-camsys_rawcf#clock-controller@1b000000mediatek,mt8192-ipesysflarb@1b00f000mediatek,mt8192-smi-larb^o7sapbsmi, Hlarb@1b10f000mediatek,mt8192-smi-larb^o7sapbsmi, Gclock-controller@1f000000mediatek,mt8192-mdpsysflarb@1f002000mediatek,mt8192-smi-larb ^o7sapbsmi, <thermal-zonescpu0-thermalJtripstrip-alertLpassiveKtrip-crit criticalcooling-mapsmap0K0 cpu1-thermalJtripstrip-alertLpassiveLtrip-crit criticalcooling-mapsmap0L0 cpu2-thermalJtripstrip-alertLpassiveMtrip-crit criticalcooling-mapsmap0M0 cpu3-thermalJtripstrip-alertLpassiveNtrip-crit criticalcooling-mapsmap0N0 cpu4-thermalJtripstrip-alertLpassiveOtrip-crit criticalcooling-mapsmap0O0cpu5-thermalJtripstrip-alertLpassivePtrip-crit criticalcooling-mapsmap0P0cpu6-thermalJtripstrip-alertLpassiveQtrip-crit criticalcooling-mapsmap0Q0cpu7-thermalJtripstrip-alertLpassiveRtrip-crit criticalcooling-mapsmap0R0vpu0-thermalStripstrip-alertLpassivetrip-crit criticalvpu1-thermalS tripstrip-alertLpassivetrip-crit criticalgpu-thermalS tripstrip-alertLpassivetrip-crit criticalgpu1-thermalS tripstrip-alertLpassivetrip-crit criticalinfra-thermalS tripstrip-alertLpassivetrip-crit criticalcam-thermalS tripstrip-alertLpassivetrip-crit criticalmd0-thermalStripstrip-alertLpassivetrip-crit criticalmd1-thermalStripstrip-alertLpassivetrip-crit criticalmd2-thermalStripstrip-alertLpassivetrip-crit criticalchosen-serial0:921600n8memory@40000000memory@ compatibleinterrupt-parent#address-cells#size-cellsmodelovl0ovl-2l0ovl-2l2rdma0rdma4serial0#clock-cellsclocksclock-divclock-multclock-output-namesphandleclock-frequencydevice_typeregenable-methodcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domainscapacity-dmips-mhz#cooling-cellscpucache-levelcache-unifiedentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptsopp-sharedopp-hzopp-microvoltdma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-ranges#power-domain-cellsclock-namesmediatek,infracfgassigned-clocksassigned-clock-parents#io-channel-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#mbox-cellsstatusresetsnvmem-cellsnvmem-cell-names#thermal-sensor-cellsreset-names#pwm-cellsinterrupts-extendedinterrupt-namesphyswakeup-sourcemediatek,syscon-wakeupmediatek,apmixedsysmediatek,topckgenpower-domainsbus-rangeinterrupt-map-maskinterrupt-map#phy-cellspower-domain-namesoperating-points-v2mboxesmediatek,gce-client-regmediatek,gce-eventsmediatek,larb-idmediatek,smiiommusmediatek,rdma-fifo-sizephy-namesmediatek,larbs#iommu-cellsmediatek,scppolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-path