T8H( H4mediatek,mt8395-evkmediatek,mt8395mediatek,mt8195 +"7MediaTek Genio 1200 EVK-P1V2-EMMCaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/mailbox@10320000T/soc/mailbox@10330000Y/soc/hdr-engine@1c114000`/soc/mutex@1c016000g/soc/mutex@1c101000n/soc/vpp-merge@1c10c000u/soc/vpp-merge@1c10d000|/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/serial@11001100/soc/ethernet@11021000cpus+cpu@0cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@100cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@200cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@300cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@400cpuarm,cortex-a78 psci-f=P`m@@ cpu@500cpuarm,cortex-a78 psci-f=P`m@@cpu@600cpuarm,cortex-a78 psci-f=P`m@@cpu@700cpuarm,cortex-a78 psci-f=P`m@@cpu-mapcluster0core0 core1 core2 core3 core4 core5core6core7idle-statespscicpu-retention-larm,idle-state2*_:Dcpu-retention-barm,idle-state-*:cpu-off-larm,idle-state7*:Hcpu-off-barm,idle-state2*:l2-cache0cacheKbo@Wl2-cache1cacheKbo@Wl3-cachecacheKb o@Wdsu-pmu arm,dsu-pmue p ufaildmic-codec dmic-codec|mt8195-sound udisabledfixed-factor-clock-13mfixed-factor-clockclk13m)oscillator-26m fixed-clock-clk26moscillator-32k fixed-clock-clk32kperformance-controller@11bc10mediatek,cpufreq-hw  0 opp-table-gpuoperating-points-v2oopp-390000000 > hopp-410000000 p opp-431000000  opp-473000000 1h@ <opp-515000000 F <opp-556000000 !# Ҧopp-598000000 # opp-640000000 &% opp-670000000 'c opp-700000000 )' Lopp-730000000 + }opp-760000000 -L `opp-790000000 /q 4opp-820000000 05 opp-850000000 2 @opp-880000000 4s qpmu-a55arm,cortex-a55-pmu epmu-a78arm,cortex-a78-pmu epsci arm,psci-1.0smctimerarm,armv8-timer @e   soc+ simple-bus!(interrupt-controller@c000000 arm,gic-v33D [    e ppi-partitionsinterrupt-partition-0p interrupt-partition-1p syscon@10000000 mediatek,mt8195-topckgensysconsyscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfdysyscon@10003000mediatek,mt8195-pericfgsyscon0Bpinctrl@10005000mediatek,mt8195-pinctrlPBiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint[e3audio-default-pinspins-cmd-dat4=>ABCDEFGHIJKdisp-pwm1-default-pinspins1hedp-panel-12v-en-pinspins1`edp-panel-3v3-en-pinspins1eth-default-pins>pins-ccUVWXpins-mdioYZpins-power[\pins-rxdQRSTpins-txdMNOPeth-sleep-pins?pins-ccUVWXpins-mdioYZpins-rxdQRSTpins-txdMNOPgpio-keys-pinspinsji2c0-pins\pins i2c1-pins]pins  i2c2-pins`pins  i2c6-pinsXpinsmmc0-default-pinsDpins-clkz'fpins-cmd-dat$~}|{wvutyepins-rstxemmc0-uhs-pinsEpins-clkz'fpins-cmd-dat$~}|{wvutyepins-ds'fpins-rstxemmc1-default-pinsHpins-clko'fpins-cmd-datnpqrsemmc1-uhs-pinsIpins-clko'fpins-cmd-datnpqrsemt6360-pinsYpinspcie0-default-pinsSpins pcie0-idle-pinsTpins6pcie1-default-pinsVpins pwm0-default-pins5pins-cmd-dataspi1-pins6pinsspi-pins9pinstouch-pins_pins-irqpins-resetuart0-pins0pinsbcuart1-pins1pinsdefgsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+A,power-domain@8+AUpower-domain@9 cmfgalto+Apower-domain@10 Apower-domain@11 Apower-domain@12 Apower-domain@13 Apower-domain@14Apower-domain@15 @AK   cvppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18o+Apower-domain@24cvdec1-0oApower-domain@27 cvenc1-larboApower-domain@168$%&'()Dcvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5o+Apower-domain@17cvppsys1vppsys1-0vppsys1-1oApower-domain@22     $cwepsys-0wepsys-1wepsys-2wepsys-3oApower-domain@23!cvdec0-0oApower-domain@25"cvdec2-0oApower-domain@26# cvenc0-larboApower-domain@18 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udisabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbusuokay?0Idefaultserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbusuokay?1Idefaultserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbus udisabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbus udisabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbus udisabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbus udisabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc cmain udisabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon0(spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+ecparent-clksel-clkspi-clk udisabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap 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udisabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a@emacirq.caxiapbmac_mainptp_refrmii_internalmac_cg0((RST( RST,:;"<5@Kuokay Xrgmii-rxida= l] |''Idefaultsleep?>?mdiosnps,dwmac-mdio+eth-phy0@1ethernet-phy-id001c.c916=stmmac-axi-config:rx-queues-config;queue0%queue1%queue2%queue3%tx-queues-config=S<queue0eqqueue1eqqueue2eqqueue3equsb@11201000#mediatek,mt8195-mtu3mediatek,mtu3  - > macippc! ?+e/Bcsys_ckref_ckmcu_ck@A BguokayCusb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimace,-$/B$csys_ckref_ckmcu_ckdma_ckxhci_ckuokaymmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #ecsourcehclksource_cguokayIdefaultstate_uhs?DE    L F +G 8mmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc $e$csourcehclksource_cguokayIdefaultstate_uhs?HI  F W d r  J +K 8mmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %e Icsourcehclksource_cg  udisabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu'e,W23$clvts-calib-data-1lvts-calib-data-2tusb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ))> macippceLM./$(($csys_ckref_ckmcu_ckdma_ckxhci_ck BhuokayCusb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 *-*> macippc!*?+e0((csys_ckref_ckmcu_ckN BiuokayCusb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimace1(csys_ckuokayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 +-+> macippc!+?+e2(( csys_ckref_ckmcu_ckO BjuokayCusb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimace3( csys_ckuokaypcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ pcie-mace y8!  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Nt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!uokayusb-phy@0cref Odsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx0_pll  udisableddsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx1_pll  udisabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "eW; cmaindma+ udisabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "eW; cmaindma+uokay-?XIdefaultpmic@34mediatek,mt63604 eIRQB[3?Ychargermediatek,mt6360-chg @usb-otg-vbus-regulator "usb-otg-vbus1C(IXregulatormediatek,mt6360-regulator Zbuck1 "emi_vdd21I  }buck2 "emi_vddq1I  }Zldo1 "tp1_p3v012ZI2Z}^ldo2 "panel1_p1v81w@Iw@ldo3"vmc_pmu1OI6Kldo5 "vmch_pmu1)2I6Jldo6 "mt6360_ldo11 I ldo7 "emi_vmddr_en1 I }i2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "eW; cmaindma+ udisabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s0Wi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "e[; cmaindma+uokay-?\Idefaulti2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "e[; cmaindma+uokay-?]Idefaulttouchscreen@5dgoodix,gt9271]    ^Idefault?_i2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "e[; cmaindma+uokay-?`Idefaulti2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 0"e[; cmaindma+ udisabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c @"e[; cmaindma+ udisabledclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wP[t-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!,uokayusb-phy@0  crefda_ref Lusb-phy@700 crefda_ref Wabccintrrx_imptx_imp  $Mt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!uokayusb-phy@0  crefda_ref @usb-phy@700 crefda_ref Wdefcintrrx_imptx_imp Aphy@11e80000mediatek,mt8195-pcie-physifWghijklmGcglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1, uokayQufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy cunipromp  udisabledgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm@n0e jobmmugpu 8o(, , , , , Lcore0core1core2core3core4 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display@14f0e000mediatek,mt8195-mdp3-hdr _p display@14f0f000mediatek,mt8195-mdp3-hdr _p display@14f10000mediatek,mt8195-mdp3-hdr _p  display@14f11000mediatek,mt8195-mdp3-aalei _p ,display@14f12000mediatek,mt8195-mdp3-aal ej _p ,display@14f13000mediatek,mt8195-mdp3-aal0ek _p 0!,display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz@ _p @ wdisplay@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszP _p P w$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz` _p ` w%display@14f17000mediatek,mt8195-mdp3-tdshpp _p pdisplay@14f18000mediatek,mt8195-mdp3-tdshp _p (display@14f19000mediatek,mt8195-mdp3-tdshp _p )display@14f1a000mediatek,mt8195-mdp3-merge _p ,display@14f1b000mediatek,mt8195-mdp3-merge _p ,display@14f1c000mediatek,mt8195-mdp3-coloret _p ,display@14f1d000mediatek,mt8195-mdp3-color _p eu,display@14f1e000mediatek,mt8195-mdp3-colorev _p ,display@14f1f000mediatek,mt8195-mdp3-ovlew _p , display@14f20000mediatek,mt8195-mdp3-padding _p ,display@14f21000mediatek,mt8195-mdp3-padding _p ,display@14f22000mediatek,mt8195-mdp3-padding  _p ,dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot0 _p 0 w , dma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot@ _p @ w , dma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotP _p P w r, clock-controller@15000000mediatek,mt8195-imgsys%larb@15001000mediatek,mt8195-smi-larb  %%%  capbsmigals,smi@15002000mediatek,mt8195-smi-sub-common %%capbsmigals0 s,smi@15003000mediatek,mt8195-smi-sub-common0%%% capbsmigals0 ,clock-controller@15110000 mediatek,mt8195-imgsys1_dip_toplarb@15120000mediatek,mt8195-smi-larb  %capbsmi,clock-controller@15130000mediatek,mt8195-imgsys1_dip_nrclock-controller@15220000mediatek,mt8195-imgsys1_wpe"larb@15230000mediatek,mt8195-smi-larb#  %capbsmi,clock-controller@15330000mediatek,mt8195-ipesys3&larb@15340000mediatek,mt8195-smi-larb4  &&capbsmi,zclock-controller@16000000mediatek,mt8195-camsys'larb@16001000mediatek,mt8195-smi-larb  ''' capbsmigals,larb@16002000mediatek,mt8195-smi-larb   ''capbsmi,{smi@16004000mediatek,mt8195-smi-sub-common@'''capbsmigals0 ,smi@16005000mediatek,mt8195-smi-sub-commonP''capbsmigals0 s,larb@16012000mediatek,mt8195-smi-larb   capbsmi, |larb@16013000mediatek,mt8195-smi-larb0  capbsmi, larb@16014000mediatek,mt8195-smi-larb@  capbsmi,!larb@16015000mediatek,mt8195-smi-larbP  capbsmi,!clock-controller@1604f000mediatek,mt8195-camsys_rawaclock-controller@1606f000mediatek,mt8195-camsys_yuvaclock-controller@1608f000mediatek,mt8195-camsys_rawbclock-controller@160af000mediatek,mt8195-camsys_yuvb clock-controller@16140000mediatek,mt8195-camsys_mrawlarb@16141000mediatek,mt8195-smi-larb  '' capbsmigals,"larb@16142000mediatek,mt8195-smi-larb   capbsmi,"clock-controller@17200000mediatek,mt8195-ccusys larb@17201000mediatek,mt8195-smi-larb   capbsmi,}video-codec@18000000mediatek,mt8195-vcodec-dec q + @!`video-codec@2000mediatek,mtk-vcodec-lat-soc  rr A!!cselvdeclattopA,video-codec@10000mediatek,mtk-vcodec-late0  A!!cselvdeclattopA,video-codec@25000mediatek,mtk-vcodec-corePeP  AcselvdeclattopA,larb@1800d000mediatek,mt8195-smi-larb  !!capbsmi,larb@1800e000mediatek,mt8195-smi-larb  !capbsmi,clock-controller@1800f000mediatek,mt8195-vdecsys_soc!larb@1802e000mediatek,mt8195-smi-larb  capbsmi,clock-controller@1802f000mediatek,mt8195-vdecsyslarb@1803e000mediatek,mt8195-smi-larb  "capbsmi,clock-controller@1803f000mediatek,mt8195-vdecsys_core1"clock-controller@190f3000mediatek,mt8195-apusys_pll0clock-controller@1a000000mediatek,mt8195-vencsys#larb@1a010000mediatek,mt8195-smi-larb  ##capbsmi,video-codec@1a020000mediatek,mt8195-vcodec-encH `abcdvwxyeU q# cvenc_sel@,+jpgdec-mastermediatek,mt8195-jpgdec,0 mnrstu+!jpgdec@1a040000mediatek,mt8195-jpgdec-hw0 mnrstueW#cjpgdec,jpgdec@1a050000mediatek,mt8195-jpgdec-hw0 mnrstueX#cjpgdec,jpgdec@1b040000mediatek,mt8195-jpgdec-hw0 rrrrrre\cjpgdec,clock-controller@1b000000mediatek,mt8195-vencsys_core1syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon  _jpgenc-mastermediatek,mt8195-jpgenc, rrrr+!jpgenc@1a030000mediatek,mt8195-jpgenc-hw ghileV#cjpgenc,jpgenc@1b030000mediatek,mt8195-jpgenc-hw rrrre[cjpgenc,larb@1b010000mediatek,mt8195-smi-larb  s  capbsmigals,~ovl@1c0000002mediatek,mt8195-disp-ovlmediatek,mt8183-disp-ovle|,  _rdma@1c002000mediatek,mt8195-disp-rdma e~,  _ color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color0e, _0ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr@e, _@aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aalPe, _Pgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma`e, _`dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-ditherpe,  _pdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsie,*cenginedigitalhs dphy udisableddsc@1c009000mediatek,mt8195-disp-dsce, _dsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi e,+cenginedigitalhs dphy udisabledmerge@1c014000mediatek,mt8195-disp-merge@e, _@dp-intf@1c015000mediatek,mt8195-dp-intfPe,cpixelenginepll udisabledmutex@1c016000mediatek,mt8195-disp-mutex`e, _` wUlarb@1c018000mediatek,mt8195-smi-larb  ((  capbsmigals,larb@1c019000mediatek,mt8195-smi-larb  s(  capbsmigals,usyscon@1c100000mediatek,mt8195-vdosys1syscon  _y$smi@1c01b000mediatek,mt8195-smi-common-vdo %&)$capbsmigals0gals1,iommu@1c01f000mediatek,mt8195-iommu-vdo8 e'cbclk,mutex@1c101000mediatek,mt8195-disp-mutex vdo1_mutexe,$ cvdo1_mutex _ wlarb@1c102000mediatek,mt8195-smi-larb   $$$ capbsmigals,larb@1c103000mediatek,mt8195-smi-larb0  s$$  capbsmigals,vdma-controller@1c104000mediatek,mt8195-vdo1-rdma@e$, @ _@ dma-controller@1c105000mediatek,mt8195-vdo1-rdmaPe$, r` _P dma-controller@1c106000mediatek,mt8195-vdo1-rdma`e$, A _` dma-controller@1c107000mediatek,mt8195-vdo1-rdmape$, ra _p dma-controller@1c108000mediatek,mt8195-vdo1-rdmae$, B _ dma-controller@1c109000mediatek,mt8195-vdo1-rdmae$, rb _ dma-controller@1c10a000mediatek,mt8195-vdo1-rdmae$, C _ dma-controller@1c10b000mediatek,mt8195-vdo1-rdmae$, rc _ vpp-merge@1c10c000mediatek,mt8195-disp-mergee$ $cmergemerge_async, _ ,$vpp-merge@1c10d000mediatek,mt8195-disp-mergee$ $cmergemerge_async, _ ,$vpp-merge@1c10e000mediatek,mt8195-disp-mergee$ $cmergemerge_async, _ ,$vpp-merge@1c10f000mediatek,mt8195-disp-mergee$ $cmergemerge_async, _ ,$vpp-merge@1c110000mediatek,mt8195-disp-mergee$ $cmergemerge_async, _ ,$dp-intf@1c113000mediatek,mt8195-dp-intf0e,$/$cpixelenginepll udisabledhdr-engine@1c114000mediatek,mt8195-disp-ethdrp@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp _@Pph$%$ $#$!$$$"$1$&$'$($)$*cmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top, rdree(,$3$4$5$6$7E3vdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncedp-tx@1c500000mediatek,mt8195-edp-txPWcdp_calibration_data,e  udisableddp-tx@1c600000mediatek,mt8195-dp-tx`Wcdp_calibration_data,e  udisabledthermal-zonescpu0-thermal  ! 7tripstrip-alert GL Spassivetrip-crit G S criticalcooling-mapsmap0 ^0 c cpu1-thermal  ! 7tripstrip-alert GL Spassivetrip-crit G S criticalcooling-mapsmap0 ^0 c cpu2-thermal  ! 7tripstrip-alert GL Spassivetrip-crit G S criticalcooling-mapsmap0 ^0 c cpu3-thermal  ! 7tripstrip-alert GL Spassivetrip-crit G S criticalcooling-mapsmap0 ^0 c cpu4-thermal  ! 7tripstrip-alert GL Spassivetrip-crit G S criticalcooling-mapsmap0 ^0 c cpu5-thermal  ! 7tripstrip-alert GL Spassivetrip-crit G S criticalcooling-mapsmap0 ^0 c cpu6-thermal  ! 7tripstrip-alert GL Spassivetrip-crit G S criticalcooling-mapsmap0 ^0 c cpu7-thermal  ! 7tripstrip-alert GL Spassivetrip-crit G S criticalcooling-mapsmap0 ^0 c vpu0-thermal  ! 7tripstrip-alert GL Spassivetrip-crit G S criticalvpu1-thermal  ! 7 tripstrip-alert GL Spassivetrip-crit G S criticalgpu-thermal  ! 7 tripstrip-alert GL Spassivetrip-crit G S criticalgpu1-thermal  ! 7 tripstrip-alert GL Spassivetrip-crit G S criticalvdec-thermal  ! 7 tripstrip-alert GL Spassivetrip-crit G S criticalimg-thermal  ! 7 tripstrip-alert GL Spassivetrip-crit G S criticalinfra-thermal  ! 7tripstrip-alert GL Spassivetrip-crit G S criticalcam0-thermal  ! 7tripstrip-alert GL Spassivetrip-crit G S criticalcam1-thermal  ! 7tripstrip-alert GL Spassivetrip-crit G S criticalchosen rserial0:921600n8firmwareopteelinaro,optee-tzsmcmemory@40000000memory@reserved-memory+!optee@43200000 ~C memory@50000000shared-dma-poolP ~*memory@53000000shared-dma-poolS@memory@54600000 ~T` memory@60000000shared-dma-pool` ~memory@62000000shared-dma-poolb@backlight-lcd0pwm-backlight   /   @backlight-lcd1pwm-backlight   .   @can-clk fixed-clock-1-can-clk7regulator-0regulator-fixed"edp_panel_3v312ZI2Z  wIdefault?regulator-1regulator-fixed"edp_backlight_12v1I  w`Idefault?gpio-keys gpio-keysbutton-volume-up d j volume_up sregulator-2regulator-fixed "wifi_3v312ZI2Z w } compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7serial0ethernet0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxoutput-highdrive-strengthinput-enableinput-disablebias-disablebias-pull-updrive-strength-microampbias-pull-downoutput-low#power-domain-cellsdomain-supplyclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extended#io-channel-cellsmediatek,mic-type-0mediatek,mic-type-1mediatek,mic-type-2regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-compatible#iommu-cells#mbox-cellsmemory-regionpower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-0pinctrl-namesnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsmediatek,pad-selectcs-gpiosspi-max-frequencyvdd-supplyxceiver-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlesnps,reset-gpiosnps,reset-delays-usmediatek,tx-delay-psmediatek,mac-wolpinctrl-1snps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphyswakeup-sourcemediatek,syscon-wakeupvusb33-supplybus-widthcap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmcbus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapbits#phy-cellsrichtek,vinovp-microvoltLDO_VIN3-supplyirq-gpiosreset-gpiosAVDD28-supplymediatek,force-modeoperating-points-v2power-domain-namesmediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathno-mappwmsenable-gpiosbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-active-highdebounce-intervallabellinux,code