YB8J(RJ&friendlyarm,nanopc-t6rockchip,rk3588 +7FriendlyElec NanoPC-T6aliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/mmc@fe2e0000/mmc@fe2c0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0cpuarm,cortex-a55 psci0 7 G0,\ ly@@  cpu@100cpuarm,cortex-a55 psci0 \ ly@@ cpu@200cpuarm,cortex-a55 psci0 \ ly@@ cpu@300cpuarm,cortex-a55 psci0 \ ly@@ cpu@400cpuarm,cortex-a76 psci0 7 G0,\ ly@@cpu@500cpuarm,cortex-a76 psci0 \ ly@@cpu@600cpuarm,cortex-a76 psci0 7 G0,\ ly@@cpu@700cpuarm,cortex-a76 psci0 \ ly@@ idle-states%pscicpu-sleeparm,idle-state2CZdkx{ l2-cache-l0cachen{@ l2-cache-l1cachen{@l2-cache-l2cachen{@l2-cache-l3cachen{@l2-cache-b0cachen{@l2-cache-b1cachen{@l2-cache-b2cachen{@l2-cache-b3cachen{@l3-cachecachen0{@display-subsystemrockchip,display-subsystemfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smc+protocol@14  protocol@16 pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫splltimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram +sram@0arm,scmi-shmem gpu@fb000000*rockchip,rk3588-maliarm,mali-valhall-csf 7 G 0corecoregroupstacks 0\]^ jobmmugpu( 6okay!="usb@fc000000rockchip,rk3588-dwc3snps,dwc3 @0ref_clksuspend_clkbus_clkIhost Q#$Vusb2-phyusb3-phy `utmi_wide( iRp6okayportendpoint,%usb@fc800000"rockchip,rk3588-ehcigeneric-ehci 0&Q'Vusb( 6okayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci 0&Q'Vusb( 6okayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci 0(Q)Vusb( 6okayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci 0(Q)Vusb( 6okayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3 @(0jihkr&ref_clksuspend_clkbus_clkutmipipeIhostQ* Vusb3-phy `utmi_widei4p< 6disablediommu@fc900000 arm,smmu-v3 @qsvoeventqgerrorpriqcmdq-syncV 6disablediommu@fcb00000 arm,smmu-v3 @}{eventqgerrorpriqcmdq-syncV 6disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfd Xosyscon@fd58c000rockchip,rk3588-sys-grfsyscon Xjsyscon@fd5a4000rockchip,rk3588-vop-grfsyscon Z@ ksyscon@fd5a6000rockchip,rk3588-vo0-grfsyscon Z` 0syscon@fd5a8000rockchip,rk3588-vo1-grfsyscon Z@0lsyscon@fd5ac000rockchip,rk3588-usb-grfsyscon Z@syscon@fd5b0000rockchip,rk3588-php-grfsyscon [,syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon [syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon \@syscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsyscon \@syscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ]@+usb2phy@0rockchip,rk3588-usb2phy 0phyclk usb480m_phy0imcphyapb6okayotg-porto6okay#syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ]@+usb2phy@8000rockchip,rk3588-usb2phy 0phyclk usb480m_phy2iocphyapb6okay&host-porto6okayz+'syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ]@+usb2phy@c000rockchip,rk3588-usb2phy 0phyclk usb480m_phy3ip cphyapb6okay(host-porto6okay)syscon@fd5e0000$rockchip,rk3588-hdptxphy-grfsyscon ^syscon@fd5f0000rockchip,rk3588-iocsyscon _sram@fd600000 mmio-sram ``+clock-controller@fd7c0000rockchip,rk3588-cru |7]q@GA.2Fq)׫ׄe/ׄ eZ р ,i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c =0ts i2cpclk-default+6okayregulator@42rockchip,rk8602 Bvdd_cpu_big0_s0dp,A.regulator-state-memLregulator@43 rockchip,rk8603rockchip,rk8602 Cvdd_cpu_big1_s0dp,A.regulator-state-memLserial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uart K0baudclkapb_pclke//jtxrx0defaultt~ 6disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm 0 pwmpclk1default 6disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm 0 pwmpclk2default6okaypwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 0 pwmpclk3default 6disabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm 00 pwmpclk4default 6disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfd mpower-controller!rockchip,rk3588-power-controller+6okay power-domain@8 +power-domain@9  0!#" 567+power-domain@10 0!#"8power-domain@11 0!#"9power-domain@12 0:;<=power-domain@13 +power-domain@14 (0>power-domain@15  0?power-domain@16 0 @AB+power-domain@17  0 CDEpower-domain@21 0 FGHIJKLM+power-domain@23 0CANpower-domain@14  0>power-domain@15 0?power-domain@22 0Opower-domain@24 0[Z]PQ+power-domain@25 80ZRpower-domain@26 80QSTpower-domain@27 00UVWX+power-domain@28  0YZpower-domain@29 (0[\power-domain@30 0z{]power-domain@31 @0W^_`apower-domain@33 !0WZ[power-domain@34 "0WZ[power-domain@37 %02bpower-domain@38 &045power-domain@40 (cvideo-codec@fdb50000+rockchip,rk3588-vpu121rockchip,rk3568-vpu wvdpu0 aclkhclkd( iommu@fdb50800,rockchip,rk3588-iommurockchip,rk3568-iommu @v aclkiface0( Vdrga@fdb80000(rockchip,rk3588-rgarockchip,rk3288-rga t0aclkhclksclkirqp ccoreaxiahb( video-codec@fdba0000rockchip,rk3588-vepu121 z0 aclkhclke( iommu@fdba0800,rockchip,rk3588-iommurockchip,rk3568-iommu @y0 aclkiface( Vevideo-codec@fdba4000rockchip,rk3588-vepu121 @|0 aclkhclkf( iommu@fdba4800,rockchip,rk3588-iommurockchip,rk3568-iommu H@{0 aclkiface( Vfvideo-codec@fdba8000rockchip,rk3588-vepu121 ~0 aclkhclkg( iommu@fdba8800,rockchip,rk3588-iommurockchip,rk3568-iommu @}0 aclkiface( Vgvideo-codec@fdbac000rockchip,rk3588-vepu121 0 aclkhclkh( iommu@fdbac800,rockchip,rk3588-iommurockchip,rk3568-iommu @0 aclkiface( Vhvideo-codec@fdc70000rockchip,rk3588-av1-vpu lvdpu7ACGׄׄ0AC aclkhclk(  ivop@fdd90000rockchip,rk3588-vop  BPvopgamma-lut80]\abcd[7aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vopi( jklm 6disabledports+port@0+ port@1+ port@2+ port@3+ iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu  ~0]\ aclkifaceV(  6disabledii2s@fddc0000rockchip,rk3588-i2s-tdm 0mclk_txmclk_rxhclk7enjtx( ictx-m 6disabledi2s@fddf0000rockchip,rk3588-i2s-tdm 0445mclk_txmclk_rxhclk71enjtx( ictx-m 6disabledi2s@fddfc000rockchip,rk3588-i2s-tdm 000,mclk_txmclk_rxhclk7-enjrx( icrx-m 6disabledqos@fdf35000rockchip,rk3588-qossyscon P :qos@fdf35200rockchip,rk3588-qossyscon R ;qos@fdf35400rockchip,rk3588-qossyscon T <qos@fdf35600rockchip,rk3588-qossyscon V =qos@fdf36000rockchip,rk3588-qossyscon ` ]qos@fdf39000rockchip,rk3588-qossyscon bqos@fdf3d800rockchip,rk3588-qossyscon cqos@fdf3e000rockchip,rk3588-qossyscon _qos@fdf3e200rockchip,rk3588-qossyscon ^qos@fdf3e400rockchip,rk3588-qossyscon `qos@fdf3e600rockchip,rk3588-qossyscon aqos@fdf40000rockchip,rk3588-qossyscon [qos@fdf40200rockchip,rk3588-qossyscon  \qos@fdf40400rockchip,rk3588-qossyscon  Uqos@fdf40500rockchip,rk3588-qossyscon  Vqos@fdf40600rockchip,rk3588-qossyscon  Wqos@fdf40800rockchip,rk3588-qossyscon  Xqos@fdf41000rockchip,rk3588-qossyscon  Yqos@fdf41100rockchip,rk3588-qossyscon  Zqos@fdf60000rockchip,rk3588-qossyscon @qos@fdf60200rockchip,rk3588-qossyscon  Aqos@fdf60400rockchip,rk3588-qossyscon  Bqos@fdf61000rockchip,rk3588-qossyscon  Cqos@fdf61200rockchip,rk3588-qossyscon  Dqos@fdf61400rockchip,rk3588-qossyscon  Eqos@fdf62000rockchip,rk3588-qossyscon >qos@fdf63000rockchip,rk3588-qossyscon 0 ?qos@fdf64000rockchip,rk3588-qossyscon @ Nqos@fdf66000rockchip,rk3588-qossyscon ` Fqos@fdf66200rockchip,rk3588-qossyscon b Gqos@fdf66400rockchip,rk3588-qossyscon d Hqos@fdf66600rockchip,rk3588-qossyscon f Iqos@fdf66800rockchip,rk3588-qossyscon h Jqos@fdf66a00rockchip,rk3588-qossyscon j Kqos@fdf66c00rockchip,rk3588-qossyscon l Lqos@fdf66e00rockchip,rk3588-qossyscon n Mqos@fdf67000rockchip,rk3588-qossyscon p Oqos@fdf67200rockchip,rk3588-qossyscon r qos@fdf70000rockchip,rk3588-qossyscon 8qos@fdf71000rockchip,rk3588-qossyscon  9qos@fdf72000rockchip,rk3588-qossyscon 5qos@fdf72200rockchip,rk3588-qossyscon " 6qos@fdf72400rockchip,rk3588-qossyscon $ 7qos@fdf80000rockchip,rk3588-qossyscon Rqos@fdf81000rockchip,rk3588-qossyscon  Sqos@fdf81200rockchip,rk3588-qossyscon  Tqos@fdf82000rockchip,rk3588-qossyscon Pqos@fdf82200rockchip,rk3588-qossyscon " Qdfi@fe060000 rockchip,rk3588-dfi@&0:opcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?00CH>MR)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr#4`GppppUfu0q0}Q* Vpcie-phy( "T @ @0 @@dbiapbconfigi). cpwrpipe+6okay rsdefaulttlegacy-interrupt-controller# ppcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O00DI?NSs)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr#4`GuuuuUfu@q@}Qv Vpcie-phy( "T @ @0 A@dbiapbconfigi*/ cpwrpipe+6okay rwdefaultxlegacy-interrupt-controller# uethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a  macirqeth_wake_irq(067Y^50stmmacethclk_mac_refpclk_macaclk_macptp_ref( !i$ cstmmacethj,yz{ 6disabledmdiosnps,dwmac-mdio+stmmac-axi-config#3yrx-queues-configCzqueue0queue1tx-queues-configY{queue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci !(0b_eTosatapmaliverxoobrefasico+ 6disabledsata-port@0 @Qv Vsata-phy  sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci #(0dagVqsatapmaliverxoobrefasico+ 6disabledsata-port@0 @Q* Vsata-phy  spi@fe2b0000 rockchip,sfc +@0/0clk_sfchclk_sfc+6okaydefault|flash@0jedec,spi-nor 2mmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc ,@ 0  biuciuciu-driveciu-sample default}~( (6okay ")1?Kmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc -@ 0biuciuciu-driveciu-sample default( % 6disabledmmc@fe2e0000rockchip,rk3588-dwcmshc .7-., G n6 (0,*+-.corebusaxiblocktimer default(iccorebusaxiblocktimer6okay)X^l{i2s@fe470000rockchip,rk3588-i2s-tdm G0+/(mclk_txmclk_rxhclk7)-e//jtxrx( &i*+ ctx-mrx-mdefault6okayportendpointi2s,i2s@fe480000rockchip,rk3588-i2s-tdm H0y}umclk_txmclk_rxhclke//jtxrxi^_ ctx-mrx-mdefault( 6disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2s I0i2s_clki2s_hclk7ejtxrx( &default 6disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2s J0%i2s_clki2s_hclk7"ejtxrx( &default 6disabledinterrupt-controller@fe600000 arm,gic-v3  `h a8#+msi-controller@fe640000arm,gic-v3-its dqmsi-controller@fe660000arm,gic-v3-its fppi-partitionsinterrupt-partition-0interrupt-partition-1 dma-controller@fea10000arm,pl330arm,primecell @ VW0n apb_pclk /dma-controller@fea30000arm,pl330arm,primecell @ XY0o apb_pclk i2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c 0{ i2cpclk>default+ 6disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0| i2cpclk?default+6okayregulator@42rockchip,rk8602 B vdd_npu_s0dp~,A.regulator-state-memLi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0} i2cpclk@default+ 6disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0~ i2cpclkAdefault+ 6disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0 i2cpclkBdefault+ 6disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !0TW pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt 0dc tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spi F0spiclkapb_pclke//jtxrx  default+ 6disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spi G0spiclkapb_pclke//jtxrx  default+ 6disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spi H0spiclkapb_pclkejtxrx default+6okay7G pmic@0rockchip,rk806B@  default $ <. H. T. `. l. x. . . . .  .   .  dvs1-null-pins gpio_pwrctrl1 pin_fun0dvs2-null-pins gpio_pwrctrl2 pin_fun0dvs3-null-pins gpio_pwrctrl3 pin_fun0regulatorsdcdc-reg1dp~,0 vdd_gpu_s0 "regulator-state-memLdcdc-reg2dp~,0vdd_cpu_lit_s0regulator-state-memLdcdc-reg3 L q,0 vdd_log_s0regulator-state-memL ; qdcdc-reg4dp~,0 vdd_vdenc_s0regulator-state-memLdcdc-reg5 L ,0 vdd_ddr_s0regulator-state-memL ; Pdcdc-reg6 vdd2_ddr_s3regulator-state-mem Wdcdc-reg7,0vdd_2v0_pldo_s3regulator-state-mem W ;dcdc-reg82Z2Z vcc_3v3_s3regulator-state-mem W ;2Zdcdc-reg9 vddq_ddr_s0regulator-state-memLdcdc-reg10w@w@ vcc_1v8_s3regulator-state-mem W ;w@pldo-reg1w@w@ avcc_1v8_s0regulator-state-memLpldo-reg2w@w@ vcc_1v8_s0regulator-state-memL ;w@pldo-reg3OO avdd_1v2_s0regulator-state-memLpldo-reg42Z2Z,0 vcc_3v3_s0regulator-state-memLpldo-reg5w@2Z,0 vccio_sd_s0regulator-state-memLpldo-reg6w@w@ pldo6_s3regulator-state-mem W ;w@nldo-reg1 q q vdd_0v75_s3regulator-state-mem W ; qnldo-reg2 P Pvdd_ddr_pll_s0regulator-state-memL ; Pnldo-reg3 q q avdd_0v75_s0regulator-state-memLnldo-reg4 P P vdd_0v85_s0regulator-state-memLnldo-reg5 q q vdd_0v75_s0regulator-state-memLspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spi I0spiclkapb_pclkejtxrx  default+ 6disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uart L0baudclkapb_pclke// jtxrxdefault~t 6disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uart M0baudclkapb_pclke/ / jtxrxdefault~t6okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uart N0baudclkapb_pclke/ / jtxrxdefault~t 6disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uart O0baudclkapb_pclke jtxrxdefault~t 6disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uart P0baudclkapb_pclke jtxrxdefault~t 6disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uart Q0baudclkapb_pclke jtxrxdefault~t 6disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uart R0baudclkapb_pclkennjtxrxdefault~t 6disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uart S0baudclkapb_pclken n jtxrxdefault~t 6disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uart T0baudclkapb_pclken n jtxrxdefault~t 6disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm 0LK pwmpclkdefault 6disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm 0LK pwmpclkdefault 6disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 0LK pwmpclkdefault 6disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm 00LK pwmpclkdefault 6disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm 0ON pwmpclkdefault 6disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm 0ON pwmpclkdefault 6disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 0ON pwmpclkdefault 6disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm 00ON pwmpclkdefault 6disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm 0RQ pwmpclkdefault 6disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm 0RQ pwmpclkdefault 6disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 0RQ pwmpclkdefault 6disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm 00RQ pwmpclkdefault 6disabledthermal-zonespackage-thermal o  tripspackage-crit 8  criticalbigcore0-thermal od  tripsbigcore0-alert L passivebigcore0-crit 8  criticalcooling-mapsmap0  bigcore2-thermal od  tripsbigcore2-alert L passivebigcore2-crit 8  criticalcooling-mapsmap0   littlecore-thermal od  tripslittlecore-alert L passivelittlecore-crit 8  criticalcooling-mapsmap0 0 center-thermal o  tripscenter-crit 8  criticalgpu-thermal od  tripsgpu-alert L passivegpu-crit 8  criticalcooling-mapsmap0  npu-thermal o  tripsnpu-crit 8  criticaltsadc@fec00000rockchip,rk3588-tsadc 0tsadcapb_pclk7GiVWctsadc-apbtsadc     gpiootpout !6okayadc@fec10000rockchip,rk3588-saradc  70saradcapb_pclkiU csaradc-apb6okay I i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c 0 i2cpclkCdefault+6okay @typec-portc@22 fcs,fusb302 " default Uconnectorusb-c-connector adual kUSB-C qsource |ports+port@0 endpoint,%port@1 endpoint,port@2 endpoint,rtc@51haoyu,hym8563 Qhym8563default  i2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c 0 i2cpclkDdefault+6okay @codec@1brealtek,rt5616 01mclk71Gportendpoint,i2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0 i2cpclkEdefault+ 6disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spi J0spiclkapb_pclken njtxrx  default+ 6disabledefuse@fecc0000rockchip,rk3588-otp  0otpapb_pclkphyarbi cotpapbarb+cpu-code@2 id@7 cpu-leakage@17 cpu-leakage@18 cpu-leakage@19 log-leakage@1a gpu-leakage@1b cpu-version@1c  npu-leakage@28 (codec-leakage@29 )dma-controller@fed10000arm,pl330arm,primecell @ Z[0p apb_pclk nphy@fed60000rockchip,rk3588-hdptx-phy 0Trefapbo8i#cde!""cphyapbinitcmnlaneroplllcpll 6disabledphy@fed80000rockchip,rk3588-usbdp-phy o0lVrefclkimmortalpclkutmi(i   cinitcmnlanepcs_apbpma_apb    6okay   r r$port+endpoint@0 ,endpoint@1 ,phy@fee00000rockchip,rk3588-naneng-combphy 0vW refapbpipe7Goi<Ccphyapb , 26okayvphy@fee20000rockchip,rk3588-naneng-combphy 0xW refapbpipe7Goi>Ecphyapb , 26okay*sram@ff001000 mmio-sram +pinctrlrockchip,rk3588-pinctrl+gpio@fd8a0000rockchip,gpio-bank 0qr  H  #S THEADER_10HEADER_08HEADER_32IR receiver [PWM3_IR_M0]gpio@fec20000rockchip,gpio-bank 0st  H  # THEADER_27HEADER_28HEADER_15HEADER_26HEADER_21HEADER_19HEADER_23HEADER_24HEADER_22HEADER_05HEADER_03gpio@fec30000rockchip,gpio-bank 0uv  H@  #. TCSI1_11CSI1_12 gpio@fec40000rockchip,gpio-bank 0wx  H`  # THEADER_35HEADER_38HEADER_40HEADER_36HEADER_37DSI0_12HEADER_33DSI0_10HEADER_07HEADER_16HEADER_18HEADER_29HEADER_31HEADER_12DSI0_08DSI0_14HEADER_11HEADER_13DSI1_10gpio@fec50000rockchip,gpio-bank 0yz  H  #C TDSI1_08DSI1_14DSI1_12CSI0_11CSI0_12rpcfg-pull-up dpcfg-pull-down qpcfg-pull-none pcfg-pull-none-drv-level-2  pcfg-pull-up-drv-level-1 d pcfg-pull-up-drv-level-2 d pcfg-pull-none-smt  auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout emmc-bus8 emmc-clk emmc-cmd emmc-data-strobe eth1fspifspim1-pins`    |gmac1gpuhdmii2c0i2c0m2-xfer -i2c1i2c1m0-xfer  i2c2i2c2m0-xfer   i2c3i2c3m0-xfer   i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2c6i2c6m0-xfer   i2c7i2c7m0-xfer   i2c8i2c8m2-xfer   i2s0i2s0-lrck i2s0-mclk i2s0-sclk i2s0-sdi0 i2s0-sdo0 i2s1i2s1m0-lrck i2s1m0-sclk i2s1m0-sdi0 i2s1m0-sdi1 i2s1m0-sdi2 i2s1m0-sdi3 i2s1m0-sdo0  i2s1m0-sdo1  i2s1m0-sdo2  i2s1m0-sdo3  i2s2i2s2m1-lrck i2s2m1-sclk  i2s2m1-sdi  i2s2m1-sdo  i2s3i2s3-lrck i2s3-sclk i2s3-sdi i2s3-sdo jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp pmupwm0pwm0m0-pins 1pwm1pwm1m1-pins  2pwm2pwm2m0-pins 3pwm3pwm3m0-pins 4pwm4pwm4m0-pins  pwm5pwm5m0-pins pwm6pwm6m0-pins  pwm7pwm7m0-pins  pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins  pwm12pwm12m0-pins  pwm13pwm13m0-pins  pwm14pwm14m0-pins  pwm15pwm15m0-pins  refclksatasata0sata1sata2sdiosdiom1-pins` sdmmcsdmmc-bus4@ sdmmc-clk }sdmmc-cmd ~sdmmc-det spdif0spdif1spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m1-pins0 spi1m1-cs0 spi1m1-cs1 spi2spi2m2-pins0  spi2m2-cs0 spi3spi3m1-pins0  spi3m1-cs0 spi3m1-cs1 spi4spi4m0-pins0 spi4m0-cs0 spi4m0-cs1 tsadctsadc-shut uart0uart0m1-xfer  0uart1uart1m1-xfer   uart2uart2m0-xfer  uart3uart3m1-xfer   uart4uart4m1-xfer   uart5uart5m1-xfer   uart6uart6m1-xfer   uart7uart7m1-xfer   uart8uart8m1-xfer   uart9uart9m1-xfer   vopbt656gpio-functsadc-gpio-func eth0gmac0gpio-ledssys-led-pin  usr-led-pin  headphonehp-det hym8563hym8563-int ir-receiverir-receiver-pin  pciepcie2-0-rst  pcie2-1-rst tpcie2-2-rst xpcie-m20-pwren pcie-m21-pwren usbtypec5v-pwren usbc0-int 4g-lte-pwren usb@fc400000rockchip,rk3588-dwc3snps,dwc3 @@0ref_clksuspend_clkbus_clkIotg QVusb2-phyusb3-phy `utmi_wide( iSp 6disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon [syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon \syscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon \@syscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ]@@+usb2phy@4000rockchip,rk3588-usb2phy @0phyclk usb480m_phy1incphyapb 6disabledotg-porto 6disabledi2s@fddc8000rockchip,rk3588-i2s-tdm ܀0mclk_txmclk_rxhclk7enjtx( ictx-m 6disabledi2s@fddf4000rockchip,rk3588-i2s-tdm @099?mclk_txmclk_rxhclk76enjtx( ictx-m 6disabledi2s@fddf8000rockchip,rk3588-i2s-tdm ߀0++'mclk_txmclk_rxhclk7(enjrx( icrx-m 6disabledi2s@fde00000rockchip,rk3588-i2s-tdm 0&&"mclk_txmclk_rxhclk7#enjrx( icrx-m 6disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+00@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr#4`GUfu}Q Vpcie-phy( "T @ @0 @@dbiapbconfigi&+ cpwrpipe6okay rlegacy-interrupt-controller# pcie-ep@fe150000rockchip,rk3588-pcie-epP @ @ @ @0dbidbi2apbaddr_spaceatu00@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipe +syspmcmsglegacyerrdma0dma1dma2dma3f}Q Vpcie-phy( "i&+ cpwrpipe 6disabledpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+00AF<KPu)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr#4`GUfu}Q Vpcie-phy( "T @ @@0 @@@dbiapbconfigi', cpwrpipe 6disabledlegacy-interrupt-controller# pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /00BG=LQ)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr#4`GUfu q }Q Vpcie-phy( "T @ @0 @@dbiapbconfigi(- cpwrpipe+6okay r wdefaultlegacy-interrupt-controller# ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a  macirqeth_wake_irq(067X]40stmmacethclk_mac_refpclk_macaclk_macptp_ref( !i# cstmmacethj, 6disabledmdiosnps,dwmac-mdio+stmmac-axi-config#3rx-queues-configCqueue0queue1tx-queues-configYqueue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci "(0c`fUpsatapmaliverxoobrefasico+ 6disabledsata-port@0 @Q Vsata-phy  phy@fed90000rockchip,rk3588-usbdp-phy o0mWrefclkimmortalpclkutmi(icinitcmnlanepcs_apbpma_apb     6disabledphy@fee10000rockchip,rk3588-naneng-combphy 0wW refapbpipe7Goi=Dcphyapb , 26okayphy@fee80000rockchip,rk3588-pcie3-phy o0ypclkiHcphy , 6okayopp-table-cluster0operating-points-v2  opp-1008000000 < L L~ @opp-1200000000 G 4 4~ @opp-1416000000 Tfr ~ @ opp-1608000000 _" P P~ @opp-1800000000 kI ~~~ @opp-table-cluster1operating-points-v2 opp-1200000000 G L LB@ @opp-1416000000 Tfr  B@ @opp-1608000000 _" B@ @opp-1800000000 kI P PB@ @opp-2016000000 x) HHB@ @opp-2208000000 h llB@ @opp-2400000000  B@B@B@ @opp-table-cluster2operating-points-v2 opp-1200000000 G L LB@ @opp-1416000000 Tfr  B@ @opp-1608000000 _" B@ @opp-1800000000 kI P PB@ @opp-2016000000 x) HHB@ @opp-2208000000 h llB@ @opp-2400000000  B@B@B@ @opp-tableoperating-points-v2!opp-300000000  L L Popp-400000000 ׄ L L Popp-500000000 e L L Popp-600000000 #F L L Popp-700000000 )' ` ` Popp-800000000 / q q Popp-900000000 5 5 5 Popp-1000000000 ; P P Padc-keys-0 adc-keys   buttons *w@ Ddbutton-maskrom kMask Rom R ]chosen wserial2:1500000n8ir-receivergpio-ir-receiver default leds gpio-ledsled-0   ksystem-led heartbeatdefault led-1   kuser-leddefault soundsimple-audio-carddefault realtek,rt5616-codec i2s  0HeadphoneHeadphonesMicrophoneMicrophone JackNHeadphonesHPOLHeadphonesHPORMIC1Microphone JackMicrophone Jackmicbias1simple-audio-card,cpu5simple-audio-card,codec5vcc12v-dcin-regulatorregulator-fixed vcc12v_dcinvcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@Avcc4v0-sys-regulatorregulator-fixed vcc4v0_sys= = A.vcc-1v1-nldo-s3-regulatorregulator-fixedvcc-1v1-nldo-s3A.vcc3v3-pcie20-regulatorregulator-fixedvcc_3v3_pcie202Z2ZAwvbus5v0-typec-regulatorregulator-fixed? defaultvbus5v0_typecLK@LK@Avcc3v3-pcie2x1l0-regulatorregulator-fixed? rdefaultvcc3v3_pcie2x1l02Z2ZAsvcc3v3-pcie30-regulatorregulator-fixed?  defaultvcc3v3_pcie302Z2ZAvcc3v3-sd-s0-regulatorregulator-fixed r2Z2Z vcc3v3_sd_s0Avdd-4g-3v3-regulatorregulator-fixed? rdefault vdd_4g_3v32Z2ZA+ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0mmc1cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namespower-domainsstatusmali-supplydr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirkusb-role-switchremote-endpointsnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosiommusreg-namesrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplyinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthfifo-depthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpno-mmcno-sdiosd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlydai-formatmclk-fsmbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-cssystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplyvbus-supplydata-rolelabelpower-rolesource-pdoswakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfmode-switchorientation-switchsbu1-dc-gpiossbu2-dc-gpiosrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesgpio-line-namesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallinux,codepress-threshold-microvoltstdout-pathlinux,default-triggersimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,hp-det-gpiosimple-audio-card,widgetssimple-audio-card,routingsound-daienable-active-high