Package: cocotb Version: 1.2.0-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 1279 Depends: python Filename: ./amd64/cocotb_1.2.0-c4m.0.0_amd64.deb Size: 199128 MD5sum: 1604001ed76b6f447426ff00d28be258 SHA1: 10aaa95c62b001b38d90cbe1a01d6dc3ec918976 SHA256: fb227ed3abd96ae7ca206defc75b5c80503f4d614f95573067b4f30b706c18f6 Section: electronics Priority: extra Description: COroutine based COsimulation TestBench cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. . cocotb is completely free, open source (under the BSD License) and hosted on GitHub. . cocotb requires a simulator to simulate the RTL. Simulators that have been tested and known to work with cocotb: . Linux Platforms * Icarus Verilog * GHDL * Aldec Riviera-PRO * Synopsys VCS * Cadence Incisive * Mentor ModelSim (DE and SE) . Windows Platform * Icarus Verilog * Aldec Riviera-PRO * Mentor ModelSim (DE and SE) . https://cocotb.readthedocs.io Package: graywolf Version: 0.1.6.191014-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 1190 Depends: libc6 (>= 2.7), libgsl23, libgslcblas0, libx11-6 Filename: ./amd64/graywolf_0.1.6.191014-c4m.0.0_amd64.deb Size: 423744 MD5sum: e854aa88622533737a7714e03de8a50e SHA1: 5d868ece99253ad3492feaec78fb6c6eb4095fc0 SHA256: 42b2e7103e85cbb0ff8b05cf451a07b321c91c75adb95d3723296cfa8e60e27c Section: electronics Priority: extra Description: Standard cell placer forked from TimberWolf graywolf is used for placement in VLSI design. It's mainly used together with qflow. . http://opencircuitdesign.com/qflow/ Package: gtkwave Version: 3.3.103.dev.r1543-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 4502 Depends: libbz2-1.0, libc6 (>= 2.14), libcairo2 (>= 1.10.0), libgcc1 (>= 1:3.0), libgdk-pixbuf2.0-0 (>= 2.22.0), libglib2.0-0 (>= 2.49.3), libgtk-3-0 (>= 3.21.5), liblzma5 (>= 5.1.1alpha+20120614), libpango-1.0-0 (>= 1.14.0), libpangocairo-1.0-0 (>= 1.14.0), libstdc++6 (>= 5.2), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0), zlib1g (>= 1:1.2.0) Filename: ./amd64/gtkwave_3.3.103.dev.r1543-c4m.0.0_amd64.deb Size: 2382648 MD5sum: e8dc0804215191c125ddbe70f66fe9ad SHA1: 2a08f057bb7efcec73b45f941b78f8c2b27bbacd SHA256: f64be2cd5eb410ebdbc2d0190b3c8b8a96cd2d4f761eebbcbfd6af846891ab50 Section: electronics Priority: extra Description: Waveform Viewer GTKWave is a waveform viewer that can view VCD files produced by most Verilog simulation tools, as well as LXT files produced by certain Verilog simulation tools. Package: iverilog Version: 11.0.dev20191104.gita621fa4-c4m.0.0 Architecture: amd64 Maintainer: Chips4Makers Installed-Size: 7 Filename: ./amd64/iverilog_11.0.dev20191104.gita621fa4-c4m.0.0_amd64.deb Size: 1208 MD5sum: e9f0efd4c1d07cc0824326970394c029 SHA1: a4c76b22ce6d060b80f8c48dc4e2bd9b7b05f8b9 SHA256: f0639e5cde55eb34abfb36892147ce52cab55a0d3ba8adf42080c93b827bded2 Section: electronics Priority: extra Description: Icarus Verilog Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard. Package: magic Version: 8.2.144-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 2616 Depends: libc6 (>= 2.2.5), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0) Filename: ./amd64/magic_8.2.144-c4m.0.0_amd64.deb Size: 964820 MD5sum: f0023f8d549a0d17c813e452357452d6 SHA1: d662222d794be5f4777642730b7690c5092f8cd3 SHA256: 2e2708786372306a2e76e0d2b774332b48a30ce0b1040f1fd7bdb666a0403467 Section: electronics Priority: extra Description: Magic detail router for digital ASIC designs Magic detail router for digital ASIC designs . http://opencircuitdesign.com/magic/ Package: netgen-lvs Source: netgen Version: 1.5.133-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 736 Depends: libc6 (>= 2.14), libtcl8.6 (>= 8.6.0) Filename: ./amd64/netgen-lvs_1.5.133-c4m.0.0_amd64.deb Size: 191104 MD5sum: 19ec27a0ee0ab72fdd5e8abe750c607e SHA1: c774c383cda7d902926bd11d9c49b7e3ef4023ea SHA256: 637906bbedf213e5f3d19d996529a25afbbc39652ccf7460aacceb266df8587a Section: electronics Priority: extra Description: Netgen complete LVS tool for comparing SPICE or verilog netlists Netgen complete LVS tool for comparing SPICE or verilog netlists . http://opencircuitdesign.com/netgen/ Package: qflow Version: 1.4.62-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 5699 Depends: libc6 (>= 2.14), yosys, graywolf, qrouter, magic, netgen-lvs Conflicts: qflow-tech-osu018, qflow-tech-osu035, qflow-tech-osu050 Filename: ./amd64/qflow_1.4.62-c4m.0.0_amd64.deb Size: 593040 MD5sum: 9d74acf376e2f17fdfbdc690940c1f2f SHA1: 1a96d85aeb7912be83a01cdaa99383e86b56ef27 SHA256: 17c99f37a3fdfbc215a5d9effd899424faaf6836775476cc77796d2dea12de1b Section: electronics Priority: extra Description: Qflow full end-to-end digital synthesis flow for ASIC designs Qflow full end-to-end digital synthesis flow for ASIC designs . http://opencircuitdesign.com/qflow/ Package: qrouter Version: 1.4.19-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 474 Depends: libc6 (>= 2.14), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0), libx11-6 Filename: ./amd64/qrouter_1.4.19-c4m.0.0_amd64.deb Size: 165780 MD5sum: b2ed86e0437239557ee7fc6cae630e14 SHA1: fb9425461b7a0f30b4601c91fdaca4577ac6546d SHA256: 9228b24f3b62b9da9dc2584abbb5389fe50bf631c58de9224de6dbf1858cd40b Section: electronics Priority: extra Description: Qrouter detail router for digital ASIC designs Qrouter detail router for digital ASIC designs . http://opencircuitdesign.com/qrouter/ Package: verilator Version: 4.020-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 15084 Depends: libc6 (>= 2.14), libgcc1 (>= 1:3.0), libstdc++6 (>= 5.2) Filename: ./amd64/verilator_4.020-c4m.0.0_amd64.deb Size: 3045884 MD5sum: 003570c02059ccc1399fd574fb841721 SHA1: 80a45de096c1c4e9e37e11a8e852690a912497de SHA256: bbc798684ded2b872f3f96df2aca758d3f554ebf8263da3fb837591e9a1b6e1b Section: electronics Priority: extra Description: A fast simulator for synthesizable Verilog Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. Package: yosys Version: 0.9+932-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 43904 Depends: libc6 (>= 2.27), libffi6 (>= 3.0.4), libgcc1 (>= 1:3.0), libreadline7 (>= 6.0), libstdc++6 (>= 5.2), libtcl8.6 (>= 8.6.0), zlib1g (>= 1:1.1.4) Filename: ./amd64/yosys_0.9+932-c4m.0.0_amd64.deb Size: 12858528 MD5sum: 96231995f778030cde952a6473d73fdd SHA1: 0d3dc00aa8982f3b6c9f97655021bd24e5f5a0ed SHA256: 12302d63fd8c336397851c634dc3c22a45d8ea146879080761ceedefed1b12ad Section: electronics Priority: extra Description: Yosys Open SYnthesis Suite This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. . Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base. . Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license). . http://www.clifford.at/yosys/