Package: cocotb Version: 1.2.0-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 1279 Depends: python Filename: ./amd64/cocotb_1.2.0-c4m.0.0_amd64.deb Size: 199120 MD5sum: 387ae0a148f41ee3b5a65e8161489a65 SHA1: 00c082f4b3fa91330882294fc500dbd429dfc9c5 SHA256: 8df80e801fcdbf64fd04a72ecc3a204694a67084a80d1b37124e30ffffaf5505 Section: electronics Priority: extra Description: COroutine based COsimulation TestBench cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. . cocotb is completely free, open source (under the BSD License) and hosted on GitHub. . cocotb requires a simulator to simulate the RTL. Simulators that have been tested and known to work with cocotb: . Linux Platforms * Icarus Verilog * GHDL * Aldec Riviera-PRO * Synopsys VCS * Cadence Incisive * Mentor ModelSim (DE and SE) . Windows Platform * Icarus Verilog * Aldec Riviera-PRO * Mentor ModelSim (DE and SE) . https://cocotb.readthedocs.io Package: graywolf Version: 0.1.6.191014-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 1230 Depends: libc6 (>= 2.29), libgsl23 (>= 2.5), libx11-6 Filename: ./amd64/graywolf_0.1.6.191014-c4m.0.0_amd64.deb Size: 421484 MD5sum: 3d557cfc8fc3c6f0f0a4747a7d948e2a SHA1: 3c7f5ba25ec0c8f2879b95b5910289c01a139f98 SHA256: c02b09aa197baf72cf5445a9a87ff58a30485eec8bf2c4e1996916f3d8477a53 Section: electronics Priority: extra Description: Standard cell placer forked from TimberWolf graywolf is used for placement in VLSI design. It's mainly used together with qflow. . http://opencircuitdesign.com/qflow/ Package: gtkwave Version: 3.3.103.dev.r1543-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 4554 Depends: libbz2-1.0, libc6 (>= 2.29), libcairo2 (>= 1.10.0), libgcc1 (>= 1:3.0), libgdk-pixbuf2.0-0 (>= 2.22.0), libglib2.0-0 (>= 2.49.3), libgtk-3-0 (>= 3.21.5), liblzma5 (>= 5.1.1alpha+20120614), libpango-1.0-0 (>= 1.14.0), libpangocairo-1.0-0 (>= 1.14.0), libstdc++6 (>= 5.2), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0), zlib1g (>= 1:1.2.0) Filename: ./amd64/gtkwave_3.3.103.dev.r1543-c4m.0.0_amd64.deb Size: 2381388 MD5sum: f5df418c4ab377bb8b3c28020fec2c66 SHA1: d6dd4bf10d44c1616da538d0c0aba4967134960e SHA256: edba8b67eaa9cff6038c3026d09540f36402d6255c0f7b4ca226fe89ddf4f143 Section: electronics Priority: extra Description: Waveform Viewer GTKWave is a waveform viewer that can view VCD files produced by most Verilog simulation tools, as well as LXT files produced by certain Verilog simulation tools. Package: iverilog Version: 11.0.dev20191104.gita621fa4-c4m.0.0 Architecture: amd64 Maintainer: Chips4Makers Installed-Size: 7 Filename: ./amd64/iverilog_11.0.dev20191104.gita621fa4-c4m.0.0_amd64.deb Size: 1208 MD5sum: e9f0efd4c1d07cc0824326970394c029 SHA1: a4c76b22ce6d060b80f8c48dc4e2bd9b7b05f8b9 SHA256: f0639e5cde55eb34abfb36892147ce52cab55a0d3ba8adf42080c93b827bded2 Section: electronics Priority: extra Description: Icarus Verilog Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard. Package: magic Version: 8.2.144-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 2632 Depends: libc6 (>= 2.2.5), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0) Filename: ./amd64/magic_8.2.144-c4m.0.0_amd64.deb Size: 964792 MD5sum: c3173c06f0bf37a874506607cfaa888c SHA1: 92d149ac35ce7a03740596867cb467e500b96aaa SHA256: f0a5af0a2a73c5fd61e65235da7f95d95f12acf8a324beca91eb2b778311fa76 Section: electronics Priority: extra Description: Magic detail router for digital ASIC designs Magic detail router for digital ASIC designs . http://opencircuitdesign.com/magic/ Package: netgen-lvs Source: netgen Version: 1.5.133-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 748 Depends: libc6 (>= 2.29), libtcl8.6 (>= 8.6.0) Filename: ./amd64/netgen-lvs_1.5.133-c4m.0.0_amd64.deb Size: 190828 MD5sum: ad5e00ed60a0bf9edab3825e665dc5ee SHA1: f319780ffa62863046202b9d8e6aad6d92f8a72f SHA256: 1d65b2ad0f0dda0f25b175c1cd02a909b9991766b325121ac7e29aadbdf9ae39 Section: electronics Priority: extra Description: Netgen complete LVS tool for comparing SPICE or verilog netlists Netgen complete LVS tool for comparing SPICE or verilog netlists . http://opencircuitdesign.com/netgen/ Package: qflow Version: 1.4.62-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 5767 Depends: libc6 (>= 2.29), yosys, graywolf, qrouter, magic, netgen-lvs Conflicts: qflow-tech-osu018, qflow-tech-osu035, qflow-tech-osu050 Filename: ./amd64/qflow_1.4.62-c4m.0.0_amd64.deb Size: 593448 MD5sum: 345bedd4272c4f578becb819663309d9 SHA1: ed7b55004b4d67e1ec6f216ec1e4d911c295b4ab SHA256: 52b0a7e85395c00ffa000f35c4a6dba2322cc5966d49d5d1e83b06d8c7c1d0eb Section: electronics Priority: extra Description: Qflow full end-to-end digital synthesis flow for ASIC designs Qflow full end-to-end digital synthesis flow for ASIC designs . http://opencircuitdesign.com/qflow/ Package: qrouter Version: 1.4.19-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 494 Depends: libc6 (>= 2.29), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0), libx11-6 Filename: ./amd64/qrouter_1.4.19-c4m.0.0_amd64.deb Size: 165796 MD5sum: 057127b06416592c32c5ca012637420e SHA1: c951b0594ddd62374056b192377b4961351c1ca9 SHA256: 35f2f29902dd681c4880c01f8f02e72a8a26f8e6d8e6693cda9fad58380acf2c Section: electronics Priority: extra Description: Qrouter detail router for digital ASIC designs Qrouter detail router for digital ASIC designs . http://opencircuitdesign.com/qrouter/ Package: verilator Version: 4.020-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 15240 Depends: libc6 (>= 2.29), libgcc1 (>= 1:3.0), libstdc++6 (>= 5.2) Filename: ./amd64/verilator_4.020-c4m.0.0_amd64.deb Size: 3087360 MD5sum: c2f4f24c41a91f1a23f79f8db4083af6 SHA1: cd76330a6a507f5fa4209532b23ded692ea560ac SHA256: 77d6b9f5cf7f93c8343861ac79970b90db737fde0e7cd567b684047dac32ff53 Section: electronics Priority: extra Description: A fast simulator for synthesizable Verilog Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. Package: yosys Version: 0.9+932-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 43712 Depends: libc6 (>= 2.29), libffi6 (>= 3.0.4), libgcc1 (>= 1:3.0), libreadline8 (>= 6.0), libstdc++6 (>= 5.2), libtcl8.6 (>= 8.6.0), zlib1g (>= 1:1.1.4) Filename: ./amd64/yosys_0.9+932-c4m.0.0_amd64.deb Size: 12875976 MD5sum: 0296744953a326a8ae8dcd21ad07aea0 SHA1: 0048b283529723a0a02bb982910c5e727b859606 SHA256: 567cb8d20b197f7085b3b3d649f3721604eb867ad6b9d07dc662c7abbae3c1cc Section: electronics Priority: extra Description: Yosys Open SYnthesis Suite This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. . Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base. . Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license). . http://www.clifford.at/yosys/